R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 99

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 10.6
Figure 10.7
High-Speed On-Chip Oscillator Control Register 2
Voltage Detection Register 2
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
b7 b6 b5 b4 b3
NOTES:
0 0 0 0
1.
2.
3.
1.
2.
3.
4.
5.
0 0
Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the FRA2 register.
Since the value after reset is 000b, set 010b to 111b on the K version products.
Do not set on the K version products.
Set the PRC3 bit in the PRCR register to 1 (enables w riting) before w riting to the VCA2 register.
When using the voltage monitor 1 reset, set the VCA26 bit to 1.
After the VCA26 bit is set from 0 to 1, the voltage detection circuit elapses for td(E-A) before starting operation.
When using the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is from 0 to 1, the voltage detection circuit elapses for td(E-A) before starting operation.
The VCA27 bit remains unchanged after softw are reset, w atchdog timer reset, and voltage monitor 2 reset.
Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure
10.11 Procedure for Enabling Reduced Internal Pow er Consum ption Using VCA20 bit .
0
0 0 0
b2 b1 b0
VCA2 Register
FRA2 Register
Bit Symbol
Bit Symbol
(b7-b3)
VCA20
(b5-b1)
VCA26
VCA27
Symbol
FRA20
FRA21
FRA22
Symbol
VCA2
FRA2
Page 77 of 501
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—
(1)
High-speed on-chip oscillator
frequency sw itching bits
Reserved bits
Internal pow er low consumption
enable bit
Reserved bits
Voltage detection 1 enable bit
Voltage detection 2 enable bit
(5)
Address
Bit Name
Address
Bit Name
0025h
0032h
(1)
(2)
(2)
(3)
The division of high-speed on-chip
oscillator clock can be selected.
b2 b1 b0
0 0 0 : Divide-by-2 mode
0 0 1 : Divide-by-3 mode
0 1 0 : Divide-by-4 mode
0 1 1 : Divide-by-5 mode
1 0 0 : Divide-by-6 mode
1 0 1 : Divide-by-7 mode
1 1 0 : Divide-by-8 mode
1 1 1 : Divide-by-9 mode
Set to 0
The LVD1ON bit in the OFS register is set to 1: 00h
Power-on reset, v oltage monitor 1 reset or the LVD1ON
bit in the OFS register is set to 0: 01000000b
0 : Disables low consumption
1 : Enables low consumption
Set to 0
0 : Voltage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled
0 : Voltage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled
After Reset
Function
Function
After Reset
00h
10. Clock Generation Circuit
(3)
(3)
(4)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW