R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 405

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
18.5
Figure 18.16
18.5.1
The CAN module contains the following four operational modes.
Figure 18.16 shows Transition between Operational Modes.
CCLK3: Bit in CCLKR register
Reset, Sleep, RetBusOff: Bits in C0CTLR register
State_Reset, State_BusOff: Bits in C0STR register
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The CAN module can enter CAN reset/initialization mode by CPU reset or setting the Reset bit in the C0CTLR
register. When setting the Reset bit to 1, check that the State_Reset bit in the C0STR register is set to 1 during
CAN reset/initialization mode. The CAN module performs the following functions:
Interface Sleep
CAN Reset/Initialization Mode
CAN Sleep Mode
CAN Operation Mode
CAN Interface Sleep Mode
Operational Modes
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CAN communication is impossible.
If the CAN module is set to CAN reset/initialization mode during transmitting a message, it is held CAN
operation mode until the transmission is completed, it loses in arbitration or an error in it is detected and it
enters CAN reset/initialization mode after the State_Reset bit in the C0STR register is set to 0.
The C0IDR, C0MCTLi (i = 0 to 15), C0ICR, C0STR, C0RECR and C0TECR registers are initialized. All
these registers are locked to prevent CPU modification.
The C0CTLR, C0CONR, C0GMR, C0LMAR and C0LMBR registers and the CAN0 message box retain
their contents and are available for CPU access.
mode
CAN
CAN Reset/Initialization Mode
Transition between Operational Modes
Page 383 of 501
CCLK3 = 1
CCLK3 = 0
Sleep = 0
initialization mode
(State_Reset = 1)
CAN Sleep mode
CAN Reset/
CPU Reset
Sleep = 1
Reset = 0
Reset = 1
Reset = 1
TEC > 255
(State_BusOff = 1)
(State_Reset = 0)
CAN Operation
Bus off state
mode
128 times on the bus or
When 11 consecutive
recessive bits are
RetBusOff = 1
monitored
18. CAN Module