R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 333

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.16
(1)
(2)
(3)
(4)
(5)
(6)
(7)
SSCRH register
SSCRH register
SSER register
Mode)
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Read receive data in SSRDR register
Read receive data in SSRDR register
Dummy read on SSRDR register
Read ORER bit in SSSR register
Read ORER bit in SSSR register
Read RDRF bit in SSSR register
Read RDRF in SSSR register
No
No
Page 311 of 501
ORER = 1 ?
ORER = 1 ?
Initialization
RDRF = 1 ?
RDRF = 1 ?
received?
Last data
Start
End
RSSTP bit ← 1
RSSTP bit ← 0
RE bit ← 0
No
No
Yes
No
Yes
Yes
Yes
Yes
Overrun
process
error
(3) When a receive error occurs, perform an error
(6) process after reading the ORER bit. Then set the
(1) After setting each register in the clock synchronous
(2) Determine whether the last 1-byte data is received.
(4) Confirm that the RDRF bit is set to 1. If the RDRF
(5)Before the last 1-byte data is received, set the
(7) Confirm that the RDRF bit is set to 1. When the
RSSTP bit to 1 and stop after the data is
received.
ORER bit to 0. Transmit/receive can not be
restarted while the ORER bit is set to 1.
serial I/O with chip select register, dummy read on
the SSRDR register is performed and receive
operation is started.
When the last 1-byte data is received, set to stop
after the data is received.
bit is set to 1, read the receive data in the SSRDR
register. If the SSRDR register is read, the RDRF
bit is automatically set to 0.
receive operation is completed, set the RSSTP bit to
0 and the RE bit to 0 before reading the last 1-byte
data. If the SSRDR register is read before setting the
RE bit to 0, the receive operation is restarted again.
16. Clock Synchronous Serial Interface