R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 271

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.99
Timer RD Start Register
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
5.
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1
TRDSTR Register of Notes on Timer RD.
When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.
When the CSEL0 bit is set to 0 and generating the compare match signal(TRDIOA0), this bit is set to 0 (count stops).
When the CSEL1 bit is set to 0 and generating the compare match signal(TRDIOA1), this bit is set to 0 (count stops).
b3 b2
TRDSTR Register in PWM3 Mode
b1 b0
0
Bit Symbol
TSTART0
TSTART1
(b7 - b4)
TRDSTR
Symbol
CSEL0
CSEL1
Page 249 of 501
(1)
—
TRD0 count start flag
TRD1 count start flag
TRD0 count operation select bit
TRD1 count operation select bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Address
Bit Name
0137h
(4)
(5)
0 : Count stops
1 : Count starts
Set this bit to 0 (count stops) in PWM3
mode
0 : Count stops at the compare
1 : Count continues at the
0 : Count stops at the compare
1 : Count continues at the
match w ith the TRDGRA0 register
compare match w ith the
TRDGRA0 register
match w ith the TRDGRA1 register
compare match w ith the
TRDGRA1 register
(3)
(2)
After Reset
11111100b
Function
14. Timers
RW
RW
RW
RW
RW
—