R5F21236KFP#U0 Renesas Electronics America, R5F21236KFP#U0 Datasheet - Page 383

• Manufacturer Part Number: R5F21236KFP#U0
• Description: IC R8C/23 MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/23r

Specifications of R5F21236KFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 17.6
Timer RA Set the timer to start counting
Timer RA Read the count status flag
Hardware LIN Read the Synch Break detection flag
Timer RA Set the timer to stop counting
Timer RA Read the count status flag
UART0 Communication via UART0
UART0 Communication via UART0
TE bit in U0C1 register ← 1
U0TB register ← 0055h
U0TB register ← ID field
TSTART bit in TRACR register ← 1
TCSTF flag in TRACR register
START bit in TRACR register ← 0
TCSTF flag in TRACR register
Example of Header Field Transmission Flowchart (2)
SBDCT flag in LINST register
Page 361 of 501
SBDCT = 1?
TCSTF = 1?
TCSTF = 0?
YES
YES
YES
A
NO
NO
NO
Timer RA generates Synch Break.
If the TRAPRE and TRA registers for
timer RA do not need to be read or
the register settings do not need to
be changed after writing 1 to the
TSTART bit, the procedure for
reading TCSTF flag = 1 can be
omitted.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the TCSTF
flag is set to 1.
The timer RA interrupt may be used
to terminate generation of Synch
Break.
One to two cycles of the CPU clock
are required after Synch Break
generation completes before the
SBDCT flag is set to 1.
After timer RA Synch Break is
generated, the timer should be made
to stop counting.
If the TRAPRE and TRA registers for
timer RA do not need to be read or
the register settings do not need to
be changed after writing 0 to the
TSTART bit, the procedure for
reading TCSTF flag = 0 can be
omitted.
Zero to one cycle of the timer RA
count source is required after timer
RA stops counting before the TCSTF
flag is set to 0.
Transmit the Synch Field.
Transmit the ID field.
17. Hardware LIN