SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

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LXT973
10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
The LXT973 is an IEEE-compliant, 2-port, Fast Ethernet PHY transceiver that directly supports
both 100BASE-TX and 10BASE-T applications. Each port provides a Media Independent
Interface (MII) for easy attachment to 10 and 100 Mbps Media Access Controllers (MACs). The
device also provides a pseudo-ECL interface per port for use with 100BASE-FX fiber networks.
The LXT973 incorporates the auto MDIX feature, allowing it to automatically switch twisted-
pair inputs and outputs.
The LXT973 is an ideal building block for systems that require two Ethernet ports, such as
Internet Protocol (IP) Telephones, Twisted-Pair (TX)-to-Fiber (FX) converter modules, and for
telecom applications, such as Telecom Central Office (TCO) and Customer Premise Equipment
(CPE) devices.
The LXT973 supports full-duplex operation at both 10 and 100 Mbps. Its operating modes can
be set using auto-negotiation, parallel detection, or manual control.
Applications
VoIP Telephone Handsets
Media Converter
— Fiber-to-Twisted-Pair
Product Features
Dual-port Fast Ethernet PHY
2.5V operation
3.3V operation I/O compatibility
Low power consumption; 250 mW per
port typical
Full 2-port MII interface with extended
registers
Auto MDI/MDIX switch over capability
Signal Quality Error (SQE) enable/disable
100BASE-FX fiber-optic capability on
both ports
Integrated transmit and receive
termination resistors
For technical assistance on this product, please call 1-800-628-8686,
or send an e-mail tosupport@mailbox.intel.com.
Datasheet
Internet Access Devices
— Cable Modem, ADSL Modem
Ethernet Backplane Connections
Supports both auto-negotiation systems
and legacy systems without auto-
negotiation capability
Support for Next Page
20 MHz Register Access
Configurable via MDIO port or external
control pins
Integrated termination resistors
100-pin Plastic Quad Flat Package (PQFP)
— LXT973QC - Commercial (0 to 70 C
ambient).
— LXT973QE - Extended (-40 to +85 C
ambient).
Order Number: 249426-002
March 2002

SLXT973QC.A2 Summary of contents

  • Page 1

    ... Signal Quality Error (SQE) enable/disable 100BASE-FX fiber-optic capability on both ports Integrated transmit and receive termination resistors For technical assistance on this product, please call 1-800-628-8686, or send an e-mail tosupport@mailbox.intel.com. Datasheet Internet Access Devices — Cable Modem, ADSL Modem Ethernet Backplane Connections Supports both auto-negotiation systems ...

  • Page 2

    ... Information in this document is provided in connection with Intel property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...

  • Page 3

    Contents 1.0 Pin Assignments and Signal Descriptions 2.0 Signal Descriptions 3.0 Functional Description 3.1 Introduction..........................................................................................................22 3.1.1 Comprehensive Functionality .................................................................22 3.2 Interface Descriptions..........................................................................................22 3.2.1 10/100 Mbps Network Interface .............................................................22 3.2.1.1 Twisted-Pair Interface ...............................................................23 3.2.1.2 MDI Crossover (MDIX) ..............................................................23 3.2.1.3 Fiber Interface ...

  • Page 4

    Contents 3.7.2 Twisted-Pair Interface ............................................................................ 33 3.7.3 Fiber Interface ........................................................................................ 34 3.7.4 Fault Detection and Reporting ............................................................... 34 3.7.5 Remote Fault.......................................................................................... 34 3.7.6 Far End Fault ......................................................................................... 34 3.8 100 Mbps Operation............................................................................................ 35 3.8.1 100BASE-X Network Operations ........................................................... 35 3.8.2 ...

  • Page 5

    ... Link Failure Criteria and Override.......................................................57 10.3 SQE (Heartbeat)..................................................................................................57 10.4 Jabber .................................................................................................................57 10.5 Polarity Correction...............................................................................................57 10.6 Dribble Bits ..........................................................................................................58 10.7 Transmit Polarity Control.....................................................................................58 10.8 PHY Address.......................................................................................................58 11.0 Clock Generation 11.1 External Oscillator ...............................................................................................59 12.0 Register Definitions 13.0 Magnetics Information 14.0 Test Specifications 15.0 Timing Diagrams 16 ...

  • Page 6

    ... Transmission with Collision .......................................................... 55 23 MII 10BASE-T DTE Mode Auto-Negotiation ....................................................... 59 24 100BASE-T DTE Mode Auto-Negotiation ........................................................... 59 25 Link Down Clock Transition................................................................................. 60 26 PHY Identifier Bit Mapping .................................................................................. 64 27 100BASE-TX Transmit Timing - 4B Mode .......................................................... 77 28 100BASE-TX Receive Timing - 4B Mode ........................................................... 78 29 100BASE-FX Transmit Timing ............................................................................ 79 30 100BASE-FX Receive Timing ............................................................................ 80 31 10BASE-T Transmit Timing (Parallel Mode) ...

  • Page 7

    ... Register Bit Descriptions .....................................................................................61 17 Control Register (Address 0)...............................................................................62 18 Status Register (Address 1) ................................................................................63 19 PHY Identification Register 1 (Address 2)...........................................................64 20 PHY Identification Register 2 (Address 3)...........................................................64 21 Auto-Negotiation Advertisement Register (Address 4)........................................65 22 Auto-Negotiation Link Partner Base Page Ability Register (Address 5) ..............66 23 Auto-Negotiation Expansion Register (Address 6)..............................................67 24 Auto-Negotiation Next Page Transmit Register (Address 7) ...

  • Page 8

    Contents 50 Power-Up Timing Parameters............................................................................. 86 51 RESET Pulse Width and Recovery Timing Parameters ..................................... 86 8 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 ...

  • Page 9

    ... Removed Table 16: 4B/5B Coding. 61 Section 12.0, “Register Definitions” Removed “multiple 11-bit registers, with” from first sentence. 64 Table 20 “PHY Identification Register 2 (Address Changed default for Register bits 3.9:4 from “001110” to “100001”. 72 Table 29 “Absolute Maximum Ratings” Supply: added V Added three table notes ...

  • Page 10

    ...

  • Page 11

    ... Please see Table 4, “LXT973 Network Interface Signal Descriptions” on page 18 Global Control & Configuration Signal Descriptions” on page 19 Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 2 Port Global Functions Clock Generator + Manchester ...

  • Page 12

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1.0 Pin Assignments and Signal Descriptions Figure 2. LXT973 Pin Assignments TXD1_2 TXD1_3 COL1 CRS1 AUTO_NEG1 AUTO_NEG0 SD_2P5V/SPEED1 SD_2P5V/SPEED0 DUPLEX1 DUPLEX0 LED_CGF0 LED_CGF1 RESET SGND REFCLK GNDD FIBER_TP1 FIBER_TP0 MDDIS1 MDDIS0 PWRDWN1 MDC1 MDIO1 ...

  • Page 13

    ... OD = Open Drain output Schmitt Triggered input Tri-State-able output Slew-rate Limited output Weak Internal Pull-up Weak Internal Pull-down. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Reference for Full 1 Type Description I Table 3 on page 17 ...

  • Page 14

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 1. LXT973 PQFP Pin List (Continued) Pin Signal Names 34 RXCLK0 35 RXER0 36 TXER0 37 TXCLK0 38 TXEN0 39 TXD0_0 40 VCCD 41 GNDD 42 TXD0_1 43 TXD0_2 44 TXD0_3 45 COL0 46 CRS0 47 VCCIO 48 GNDIO 49 LED0_1 50 LED0_2 51 LED0_3 52 ADDR4 53 ADDR3 54 ADDR2 55 ADDR1 56 TEST_0 57 TEST_1 ...

  • Page 15

    ... OD = Open Drain output Schmitt Triggered input Tri-State-able output Slew-rate Limited output Weak Internal Pull-up Weak Internal Pull-down. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Reference for Full 1 Type Description AI/AO, SL Table 4 on page 18 – ...

  • Page 16

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 2.0 Signal Descriptions Table 2. LXT973 Port 0 Signal Descriptions Pin # Signal Names 44 TXD0_3 43 TXD0_2 42 TXD0_1 39 TXD0_0 38 TXEN0 36 TXER0 37 TXCLK0 29 RXD0_3 30 RXD0_2 31 RXD0_1 32 RXD0_0 33 RXDV0 35 RXER0 34 RXCLK0 45 COL0 46 CRS0 Analog Input Analog Output Input Output Open Drain output Schmitt Triggered input Tri-State-able output Slew-rate Limited output Weak Internal Pull-up Weak Internal Pull-down ...

  • Page 17

    ... IP = Weak Internal Pull-up Weak Internal Pull-Down Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1 Type Signal Description Management Disable. When MDDIS0 is tied High, the MDIO port is completely disabled and the Hardware Control Interface pins set their respective bits at power-up and reset ...

  • Page 18

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 3. LXT973 Port 1 Signal Descriptions (Continued) Pin # Signal Names 3 COL1 4 CRS1 19 MDDIS1 22 MDC1 23 MDIO1 Analog Input Analog Output Input Output Open Drain output Schmitt Triggered input Tri-State-able output Slew-rate Limited output Weak Internal Pull-up Weak Internal Pull-Down Table 4 ...

  • Page 19

    ... The various options are defined in Register bits 27.11:10. The TxSLEW pins set the power-on value of these register bits. I Reset. This active Low input is OR’d with Control Register bit 0.15. Address <4:1>. Sets device Port 0 PHY address. Note that ADDR0 is set I internally so that Port 1 is always “1” address higher than Port 0. I Test Pins ...

  • Page 20

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 6. LXT973 Power Supply Signal Descriptions Pin # Signal Names 40, 91 VCCD 27, 47, VCCIO 84 VCCPECL 58, 73 VCCR 65, 66 VCCT 16, 41, 90, GNDD 28, 48, 83, GNDIO 95 77 GNDPECL 69, 62 GNDR 61, 70 GNDT 14 SGND Analog Input Analog Output Input Output Open Drain output, ...

  • Page 21

    ... Duplex. Sets the duplex setting of the port in Hardware mode. High is full-duplex and Low is half-duplex Fiber/Twisted-Pair. Sets the operating state of the port in Hardware mode. High is twisted-pair and Low is fiber. I Power-Down. When set High, this pin puts the relevant PHY into I power-down mode. 21 ...

  • Page 22

    ... LXT973 auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT973 automatically detects (parallel detection) the presence of either link pulses (10 Mbps PHY) or IDLE symbols (100 Mbps PHY) and sets its operating conditions accordingly. When parallel detection is used to establish link, the resulting link is at half-duplex ...

  • Page 23

    ... The LXT973 supports either 100BASE-TX or 10BASE-T connections over 100 Unshielded Twisted-Pair (UTP). Only a transformer, RJ-45, and bypass capacitors are required to complete this interface. Using Intel’s patented waveshaping technology, the transmitter shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings allow the designer to match the output waveform to the magnetic characteristics ...

  • Page 24

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.2.1.3 Fiber Interface The LXT973 provides a PECL interface that complies with the ANSI X3.166 specification. This interface is suitable for driving a fiber-optic coupler (see Fiber ports cannot be enabled via auto-negotiation and must be enabled via the Global Hardware Control Interface pins or MDIO registers ...

  • Page 25

    ... Test loopback is available for both 100BASE-TX and 10BASE-T operation. Test loopback is enabled by setting the register bits as follows: • Register bit 0. (loopback mode) Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 4 on page 26. Table 8 Table 8 on page 26 summarizes Table 8 on page 26). ...

  • Page 26

    ... LXT973. The MDIO interface consists of a physical connection, a specific protocol which runs across the connection, and an internal set of addressable registers. The physical interface consists of a data line (MDIO) and clock line (MDC), and a control line (MDDIS). The maximum speed of MDC is 20 MHz. ...

  • Page 27

    ... Pins ADDR_<4:1> determine the base address. Each port adds its port number to the base address to obtain its port address as shown in Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 49 on page 85. See Figure ...

  • Page 28

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 7. Port Address Scheme Example ADDR<4.1> = 0001 LXT973 Port 0 Port 1 3.3.8.3 Hardware Control Interface The LXT973 provides a Hardware Control Interface for applications where the MDIO is not desired. Refer to Figure 16, “LXT973 Initialization Sequence” on page 47 3 ...

  • Page 29

    ... Regardless of clock source, careful consideration should be given to physical placement, board layout, and signal routing of the source to maintain the highest possible level of signal integrity. Refer to 3.4.2.2 MDIO Clock The MII management channel (MDIO) also requires an external clock. The managed data clock (MDC) speed is a maximum of 20 MHz ...

  • Page 30

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver The lowest power operation is achieved using the global power-down pin. This active High pin powers down every circuit in the device, including all clocks. All registers are unaltered and maintained when the global PWRDWN pin is released and the registers are reloaded with the value of the last hardware reset ...

  • Page 31

    ... Page”, defined by IEEE 802.3 (Registers 4 and 5). The LXT973 also supports the optional “Next Page” function (Registers 7 and 8). Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver SPEEDx DUPLEXx 100BASE-FX is enabled in half-duplex mode. - Low Auto-negotiation is disabled ...

  • Page 32

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.6.1.1 Base Page Exchange By exchanging Base Pages, the LXT973 and its link partner communicate their capabilities to each other. Both sides must receive at least three identical base pages for negotiation to proceed. Each side finds their highest common capabilities, exchange more pages, and agree on the operating state of the line ...

  • Page 33

    ... During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link up. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Power-Up, Reset, Link Failure Start 0. 0. Auto-Neg/Parallel Detection Check Value 0 ...

  • Page 34

    ... The LXT973 supports either 100BASE-TX or 10BASE-T connections over 100 Unshielded Twisted-Pair (UTP) cable. Only a transformer, RJ-45 connector, and bypass capacitors are required to complete this interface. On the transmit side, Intel’s patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to magnetic characteristics ...

  • Page 35

    ... Start-of-Stream Delimiter (SSD) Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver shows the structure of a standard frame packet. When the MAC is not Destination and Source Packet Length Data Field Address (6 Octets each) ...

  • Page 36

    ... Protocol Sublayer Operations In the 7-layer OSI communications model, the LXT973 is a Physical Layer 1 (PHY) device. The LXT973 implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE 802 ...

  • Page 37

    ... In this event, the RXER bit in the RX Status Frame is asserted for one clock cycle when CRS is de-asserted. 3.8.4.3 Twisted-Pair PMD Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3), as well as receiving, polarity correction, and baseline wander correction functions. 3.8.4.4 ...

  • Page 38

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.8.5 Fiber PMD Sublayer The LXT973 provides a PECL interface for connection to an external fiber-optic transceiver. (The external transceiver provides the PMD function for fiber media.) The device uses an NRZI format for the fiber interface. The fiber interface operates at 100 Mbps only and does not support 10 Mbps applications ...

  • Page 39

    ... LEDs light up for approximately one second after reset de-asserts. Each LED may be configured to one of several different display modes using the LED Configuration Pins, as shown in Table 10 on page Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 63). 40. 39 ...

  • Page 40

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver The LED driver pins are open drain circuits (10 mA maximum current rating LEDx_n pin is unused, terminate with a 10K pull-up resistor. When configured for modes the LEDs blink at the rate of 100 ms to display multiple status. ...

  • Page 41

    ... DC-to-DC converters. Intel recommends filtering the power supply to the analog VCC pins of the LXT973. This has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT973, helping with line performance. Second, if the VCC planes are laid out correctly, digital switching noise is kept away from external connectors, reducing EMI problems ...

  • Page 42

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver The recommended implementation is to break the VCC plane into two sections. The digital section supplies power to the VCCD and VCCIO pins of the LXT973. The analog section supplies power to the VCCR, VCCT, VCCPECL pins. The break between the two planes should run underneath the device ...

  • Page 43

    ... Insertion loss Primary inductance Transformer isolation Differential to common mode rejection Return Loss Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 11 Min Nom Max Units Test Condition – 1:1 – – – ...

  • Page 44

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 4.2 Typical Application Circuits Figure 12 through Figure 15 on page 46 Figure 12. Power and Ground Supply Connections GNDR/GNDT VCCR/VCCT LXT973 VCCIO VCCPECL GNDPECL 44 show typical application circuits for the LXT973. SGND 0.01 F Analog Supply Plane ...

  • Page 45

    ... Figure 13. Typical Twisted-Pair Interface Port 0 LXT973 LXT973 1. The 100 2. The 100 3. Recommended 0.1 F capacitor to improve EMI performance. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver DPAP_0 1 DPAN_0 DPBP_0 1:1 2 DPBN_0 0.001 F / VCCT ...

  • Page 46

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 14. Typical Fiber Interface DPBP_n DPBN_n LXT973 DPAN_n DPAP_n SD-2P5V GNDPECL VCCPECL 1. This pin selects between 2.5V and 3.3V fiber transceivers. The figure shows the connection for a 3.3V fiber transceiver. 2. Refer to the transceiver manufacturers’ recommendations for termination circuitry. ...

  • Page 47

    ... MDIO interface. The Hardware Control Interface is monitored during Reset to set up the MDIO registers. Figure 16. LXT973 Initialization Sequence Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 12 on page 48. Power-up or Reset Read H/W Control Interface Initialize MDIO ...

  • Page 48

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 12. Mode Control Settings MDDISn Low High - - 48 RESET PWRDWN High Low MDIO Control High Low Manual Control Low Low Reset - Latch default configuration - High Low Power and reset mode Mode Datasheet Document #: 249426 Revision #: 002 Rev ...

  • Page 49

    ... High High Low 1. These pins also set the default values for Registers 0 and 4 accordingly. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 13 SPEEDx DUPLEXx 100BASE-FX is enabled in half-duplex mode. - Low Auto-negotiation is disabled 100BASE-FX is enabled in full-duplex mode ...

  • Page 50

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 13. Configuration Settings (Hardware Control Interface) (Continued) FIBER_TPn AUTO_NEGx High Low High Low High Low 1. These pins also set the default values for Registers 0 and 4 accordingly. 50 SPEEDx DUPLEXx AUTO_NEG is disabled. LXT973 port x is forced ...

  • Page 51

    ... Auto Negotiation The LXT973 PHY supports the IEEE 802.3u auto-negotiation scheme with Next Page capability. Next Page exchange utilizes Register 7 to send information and Register 8 to receive them. Next Page exchange can only occur if both ends of the link advertise their ability to exchange Next Pages ...

  • Page 52

    ... After selecting MDI or MDIX, the node waits for a specified amount of time, while evaluating its receive channel, to determine whether the other end of the link is sending link pulses or PHY- dependent data. If link pulses or PHY-dependent data are detected, it remains in that configuration. ...

  • Page 53

    ... Displaying Symbol Errors The PHY provides the MAC with an indication of errors that occur during the receive process. This output is called RXER possible to map the symbol error detection output to the RXER pin using Register bit 26.9. In normal mode (Register bit 26.9 = 0), the RXER output is active per the IEEE 802 ...

  • Page 54

    ... Once the transmit data (or IDLE symbols) are properly encoded, they are scrambled to further reduce EMI and to spread the power spectrum using an 11-bit scrambler seed. Five-seed bits are determined by global PHY address, and six-seed bits are selected by the port number. One of the 11 bits must be a “1”. ...

  • Page 55

    ... SFD SFD DA RXER Figure 21. 100BASE-TX Transmission with no Errors TXCLK TXEN TXD<3:0> P CRS COL Figure 22. 100BASE-TX Transmission with Collision TXCLK TXEN TXD<3:0> P CRS COL Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver ...

  • Page 56

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 9.0 Fiber Interface The fiber ports of the LXT973 are designed to connect to common industry standard fiber modules. The fiber ports incorporate PECL receivers and drivers, allowing for seamless integration. The LXT973 provides a separate pin for the signal detect function. If designers wish to implement this feature, they need to provide a separate signal for this function ...

  • Page 57

    ... If link pulses or data are not received for 96-130 ms, the polarity state is reset to a non-inverted state. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 33 on page 83 for SQE timing parameters. Figure 34 57 ...

  • Page 58

    ... PHY Address 10.8 The LXT973 provides four bits to set the PHY address.The least significant bit is fixed internally with Port 1 always being one address higher than Port 0. 58 Datasheet ...

  • Page 59

    ... Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver illustrate the different frequencies of clock for 10BASE-T 2.5 Mhz Clock During Auto-Negotiation and 10BASE-T Data / Idle 2.5 Mhz Clock During Auto-Negotiation and 10BASE-T Data / Idle ...

  • Page 60

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 25. Link Down Clock Transition RXCLK TXCLK 60 Link Down condition/Auto Negotiate Link Up Any Clock 2.5Mhz Clock Clock transition time will not exceed 2.5x the destination clock period. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 ...

  • Page 61

    ... Base Registers 0 through 8 are defined in accordance with the “Reconciliation Sublayer and Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-Negotiation” sections of the IEEE 802.3 specification. Additional registers are defined in accordance with the IEEE 802.3 specification for adding unique chip functions ...

  • Page 62

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 17. Control Register (Address 0) Bit Name 0.15 RESET 0.14 Loopback Speed Selection 0.13 (LSB) Auto-Negotiation 0.12 Enable 0.11 Power-Down 0.10 Isolate Restart 0.9 Auto-Negotiation 0.8 Duplex Mode 0.7 Collision Test Speed Selection 0.6 (MSB) 0 ...

  • Page 63

    ... PHY able to perform half-duplex 100BASE PHY not able to perform half-duplex 100BASE PHY able to operate at 10 Mbps in full-duplex mode 0 = PHY not able to operate at 10 Mbps full-duplex mode 1 = PHY able to operate at 10 Mbps in half-duplex mode 0 = PHY not able to operate at 10 Mbps in half-duplex 1 = PHY able to perform full-duplex 100BASE-T2 ...

  • Page 64

    ... Register Bit Descriptions. Description The PHY identifier composed of bits 19 through 24 of the OUI 6 bits containing manufacturer’s part number 4 bits containing manufacturer’s revision number for Register Bit Descriptions The Intel OUI is 00207B hex 1 Type Default RO 0013 1 Type Default RO 011110 RO 100001 ...

  • Page 65

    ... Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Description 1 = PHY is capable of Next Page exchanges 0 = PHY is not capable of Next Page exchanges Write as 0, ignore on read 1 = Remote fault remote fault. Write as 0, ignore on read Pause operation defined in Clause 40 and 27 Pause operation defined per IEEE 802 ...

  • Page 66

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 22. Auto-Negotiation Link Partner Base Page Ability Register (Address 5) Bit Name 5.15 Next Page 5.14 Acknowledge 5.13 Remote Fault 5.12 Reserved 5.12:11 Asymmetric Pause 5.10 Pause 5.9 100BASE-T4 100BASE-TX 5.8 Full-Duplex 5.7 100BASE-TX 10BASE-T 5 ...

  • Page 67

    ... Table 16 on page 61 2. Bits that Latch High (LH) or Latch Low (LL) automatically clear when read. NOTE: This table contains modifications that are selectable in Intel PHYs. These modifications are used to ease the implementation of software Next Page. See separate Intel tutorial/white-paper on the usage of Next Pages ...

  • Page 68

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 24. Auto-Negotiation Next Page Transmit Register (Address 7) (Continued) Bit Name Acknowledge 2 7.12 (ACK2) Toggle 7.11 (T) Message/Unformatted 7.10:0 Code Field 1. Refer to Table 16 on page 61 Table 25. Auto-Negotiation Link Partner Next Page Ability Register (Address 8) Bit ...

  • Page 69

    ... Table 16 on page 61 2. Register bit 16.0 is latched in from hardware pins on hardware reset. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Description 1 = Bypass Scrambler and De-scrambler 0 = Normal operation 1 = Bypass 4B/5B encoder and decoder 0 = Normal Operation ...

  • Page 70

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 27. Special Function Register (Address 27) Bit Name Line Length 27.15:13 Indicator 27.12 Reserved Per-Port Rise 27.11:10 time Control 27.9 Auto MDIX enable 27.8 Auto MDIX 27.7 Analog Loopback Loopback Detect 27.6 Enable Loopback Speed- 27 ...

  • Page 71

    ... Insertion Loss Primary Inductance Transformer Isolation Differential to common mode rejection Return Loss Rise Time Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Min Nom Max – 1:1, 1:1 – 0.0 – 0.6 350 – ...

  • Page 72

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 14.0 Test Specifications Note: Table 29 through Table 51 on page 86 represent the performance specifications of the LXT973. These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values listed in page 73 through ...

  • Page 73

    ... Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. 2. Parameter is guaranteed by design and not subject to production testing. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Sym 100BASE- Power-Down Mode I ...

  • Page 74

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 33. REFCLK Characteristics Parameter Input Low voltage Input High voltage Input Clock Frequency Tolerance Input Clock Duty Cycle 2 Input Capacitance 1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing ...

  • Page 75

    ... Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1 Sym Min Typ Transmitter V 2 ...

  • Page 76

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 38. 10BASE-T Link Integrity Timing Characteristics (Continued) Parameter Link Max Receive Timer Link Transmit Period Link Pulse Width 1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing ...

  • Page 77

    ... Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver refer to MII timings. 0ns t1 TXEN t2 ...

  • Page 78

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 28. 100BASE-TX Receive Timing - 4B Mode Twisted-Pair RXD<3:0> NOTE: Twisted-pair input default pins are as follows: DPBP/N_0 and Table 41. MII - 100BASE-TX Receive Timing Parameters - 4B Mode Parameter RXD<3:0>, RXDV, RXER setup to RXCLK High RXD<3:0>, RXDV, RXER hold from RXCLK High CRS asserted to RXD< ...

  • Page 79

    ... Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 0ns t1 TXEN ...

  • Page 80

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 30. 100BASE-FX Receive Timing DPAP/N RXD<3:0> RXCLK Table 43. 100BASE-FX Receive Timing Parameters Parameter RXD<3:0>, RXDV, RXER setup to RXCLK High RXD<3:0>, RXDV, RXER hold from RXCLK High CRS asserted to RXD<3:0>, RXDV Receive start o “J” to CRS asserted Receive start of “ ...

  • Page 81

    ... TXEN sampled to twisted-pair output (Tx latency) 1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver ...

  • Page 82

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 32. 10BASE-T Receive Timing (Parallel Mode) RXCLK RXD, RXDV, RXER CRS Twisted-Pair Input COL NOTE: Twisted-pair input default pins are as follows: DPBP/N_0 and DPAP/N_1. Table 45. MII - 10BASE-T Receive Timing Parameters (Parallel Mode) Parameter ...

  • Page 83

    ... Unjab time 1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Sym Min Typ t1 0 ...

  • Page 84

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 35. Fast Link Pulse Timing Twisted-Pair Output NOTE: Twisted-pair output default pins are as follows: DPAP/N_0 and DPBP/N_1. Figure 36. FLP Burst Timing Twisted-Pair Output NOTE: Twisted-pair output default pins are as follows: DPAP/N_0 and DPBP/N_1. ...

  • Page 85

    ... Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. 2. When operated at 2.5 MHz. Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Sym Min ...

  • Page 86

    ... Reset recovery delay is specified as a maximum value because it refers to the PHY’s guaranteed performance. - the PHY comes out of reset after a delay of No MORE Than 300 S. System designers should consider this as a minimum value. After de-asserting RESET, the MAC should delay No LESS than 300 S before accessing the MDIO port ...

  • Page 87

    ... Datasheet Document #: 249426 Revision #: 002 Rev. Date: March 1, 2002 LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 100-Pin Plastic Quad Flat Pack • Part Number: LXT973QC & LXT973QE • Temperature Range: — Commercial & — Extended: -40 to +85 C. Dim Min A – ...

  • Page 88

    ... LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Appendix A Product Ordering Information Number SLXT973QC.A2 SLXT973QE.A2 973 S LXT 88 Revision Qualification E000 Build Format E000 E001 Qualification Q S Product Revision xn Tem perature Range Internal Package Designator xxxx IXA Product Prefix LXT IXE IXF ...