SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Figure 28. 100BASE-TX Receive Timing - 4B Mode
Twisted-Pair
RXD<3:0>
NOTE: Twisted-pair input default pins are as follows: DPBP/N_0 and
Table 41. MII - 100BASE-TX Receive Timing Parameters - 4B Mode
Parameter
RXD<3:0>, RXDV, RXER setup to
RXCLK High
RXD<3:0>, RXDV, RXER hold
from RXCLK High
CRS asserted to RXD<3:0>, RXDV
Receive start of
“J” to CRS asserted
Receive start of “T” to CRS de-
asserted
Receive start of “J” to COL
asserted
Receive start of “T” to COL de-
asserted
1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to
production testing.
78
0ns
Input
t4
CRS
t3
RXDV
RXCLK
t6
COL
DPAP/N_1.
1
Sym
Min
Typ
t1
10
t2
10
t3
3
4
t4
11
t5
10
14
t6
10
t7
14
17
250ns
t5
t1
t2
t7
Test
Max
Units
Conditions
ns
ns
5
BT
16
BT
17
BT
15
BT
20
BT
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002