SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Figure 3. LXT973 Interfaces
DATA
Interface
MDIO
Management
Interface
Port LED’s
Address /
Control
3.2.1.1
Twisted-Pair Interface
The LXT973 supports either 100BASE-TX or 10BASE-T connections over 100
Unshielded Twisted-Pair (UTP). Only a transformer, RJ-45, and bypass capacitors are required to
complete this interface. Using Intel’s patented waveshaping technology, the transmitter shapes the
outgoing signal to help reduce the need for external EMI filters. Four slew rate settings allow the
designer to match the output waveform to the magnetic characteristics. Both transmit and receive
terminations are built into the LXT973. Therefore, no external components are required between
the LXT973 and the external transformer. The transmitter uses a transformer with a center tap to
help reduce power consumption.
When operating at 100 Mbps, MLT3 symbols are continuously transmitted and received. When not
transmitting data, the LXT973 generates “IDLE” symbols.
During 10 Mbps operation, LXT973 encoded data is exchanged. When no data is exchanged, the
line transmits normal link pulses to maintain link.
3.2.1.2
MDI Crossover (MDIX)
The LXT973 crossover function, which is compliant to the IEEE 802.3, clause 23 standard,
connects the transmit output of the device to the far-end receiver in a link segment. This function
can be configured via Register bits 27.9:8. Please refer to
page
52. Default mode is auto-MDIX enabled.
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
TXENn
TXDn<3:0>
TXERn
TXCLKn
DPAP/N_0
Twisted-Pair
RXCLKn
DPBP/N_0
RXDn<3:0>
Network
DPBP/N_1
RXDVn
Interface
DPAP/N_1
RXERn
CRSn
COLn
MDIOn
MDCn
MDDISn
Direct Drive
LEDn_1
LEDn_2
LEDn_3
+3.3V
VCCIO
OR
Fiber_TPn
+2.5V
VCCD
+2.5V
ADDR <4:1>
GNDD
.01uF
Section 7.0, “Auto MDI/MDIX” on
Category
23