SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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6.0
Auto Negotiation
The LXT973 PHY supports the IEEE 802.3u auto-negotiation scheme with Next Page capability.
Next Page exchange utilizes Register 7 to send information and Register 8 to receive them. Next
Page exchange can only occur if both ends of the link advertise their ability to exchange Next
Pages.
The LXT973 is configured to make Next Page exchange easier for software. When a Base Page or
Next Page is received, the Page Received Register bit 6.1 remains set until read. When Register bit
6.2 (Next Page Able) is received, it stays set until read. This bit is cleared whenever a new
negotiation occurs. This prevents the user from reading an old value in Register 6 and assuming
there is valid information in Registers 5 and 8. Additionally, Register 6 contains a new bit (Register
bit 6.5) that indicates when the current Received Page is the Base Page. This information is useful
for recognizing when next pages must be re-sent due to the start of a new negotiation process.
Register bit 16.1 and the Page Received bit (Register bit 6.1) are also cleared upon reading Register
6.
.
Table 14. Next Page Code Word Definitions
Next Page
D15
D14
D13
D12
Encoding
OUI tagged
1
a
1
0
Message
user page 1
1
a
0
0
user page 2
1
a
0
0
user page 3
1
a
0
0
user page 4
1
a
0
0
1. a is the acknowledge bit; t is the toggle bit; L is the LFSR.
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
D11
D10
D9
D8
D7
D6
t
0
0
0
0
0
t
3.10
3.11
3.12
3.13
3.14
t
2.5
2.6
2.7
2.8
2.9
t
0
0
L.8
L.7
L.6
t
L.10
L.9
L.8
L.7
L.6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
1
3.15
2.0
2.1
2.2
2.3
2.4
2.10
2.11
2.12
2.13 2.14 2.15
L.5
L.4
L.3
L.2
L.1
L.0
L.5
L.4
L.3
L.2
L.1
L.0
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