SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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4.1.6
Twisted-Pair Interface
Use the following standard guidelines for a twisted-pair interface:
Place the magnetics as close as possible to the LXT973.
Keep transmit pair traces as short as possible; both traces should have the same length.
Avoid vias and layer changes as much as possible.
Keep the transmit and receive pairs apart to avoid cross-talk.
Route the transmit pair adjacent to a ground plane. The optimum arrangement is to place the
transmit traces two to three layers from the ground plane with no intervening signals.
Improve EMI performance by filtering the TPO center tap. A single ferrite bead rated at
100 mA may be used to supply center tap current to all ports.
4.1.6.1
Magnetics Information
The LXT973 requires a 1:1 ratio for the receive transformers and a 1:1 ratio for the transmit
transformers. The transformer isolation voltage should be rated at 2 kV to protect the circuitry from
static voltages across the connectors and cables. Refer to
Before committing to a specific component, designers should contact the manufacturer for current
product specifications, and validate the magnetics for the specific application.
Table 11. Magnetics Requirements
Parameter
Rx turns ratio
Tx turns ratio
Insertion loss
Primary inductance
Transformer
isolation
Differential to
common mode
rejection
Return Loss
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Table 11
Min
Nom
Max
Units
Test Condition
1:1
1:1
0.0
0.6
1.1
dB
350
H
2
kV
40
dB
.1 to 60 MHz
35
dB
60 to 100 MHz
-16
dB
30 MHz
-10
dB
80 MHz
for transformer requirements.
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