SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Page 62/88

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LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Table 17. Control Register (Address 0)
Bit
Name
0.15
RESET
0.14
Loopback
Speed Selection
0.13
(LSB)
Auto-Negotiation
0.12
Enable
0.11
Power-Down
0.10
Isolate
Restart
0.9
Auto-Negotiation
0.8
Duplex Mode
0.7
Collision Test
Speed Selection
0.6
(MSB)
0.5:0
Reserved
1. Refer to
Table 16 on page 61
2. During a hardware reset, all LHR information is latched in from the pins. During a software reset (Register
bit 0.15), the LHR information is not re-read from the pins. This information reverts back to the information
that was read in during the hardware reset. During a hardware reset, register information is unavailable for
1 ms after de-assertion of the reset. During a software reset (Register bit 0.15) the registers are available
for reading. The reset bit should be polled to see when the part has completed reset.
3. LHR = Latched on Hardware Reset. Register bits 0.12, 0.13 and 0.8 are initialized based on the pin
configuration value.
4. The Isolate function (Register bit 0.10) tri-states all port MAC interface outputs. On the input side, TXEN
and TXER are ignored.
62
Description
1 = PHY reset
0 = Normal operation
1 = Enable loopback mode
0 = Disable loopback mode
0.6
0.13
1
1 = Reserved
1
0 = 1000 Mbps (not allowed)
0
1 = 100 Mbps
0
0 = 10 Mbps
1 = Enable Auto-Negotiation Process
0 = Disable Auto-Negotiation Process
1 = Power-Down
0 = Normal operation
1 = Electrically isolate PHY from MII
0 = normal operation
1 = Restart Auto-Negotiation Process
0 = Normal operation
1 = Full-duplex
0 = Half-duplex
1 = Enable COL signal test
0 = Disable COL signal test
0.6
0.13
1
1 = Reserved
1
0 = 1000 Mbps (not allowed)
0
1 = 100 Mbps
0
0 = 10 Mbps
Write as 0, ignore on Read
for Register Bit Descriptions.
1,2
Type
Default
R/W
0
AC
Note 2
R/W
0
LHR
R/W
Note 3
LHR
R/W
Note 3
R/W
0
0
R/W
Note 4
R/W
0
AC
LHR
R/W
Note 3
R/W
0
R/W
00
R/W
000000
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002