SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Figure 39. Power-Up Timing
VCC
MDIO,etc.
Table 50. Power-Up Timing Parameters
Parameter
Voltage threshold
2
Power-up delay
1. Typical values are at 25
2. Power-up delay is specified as a maximum value because it refers to the PHY’s guaranteed performance. -
the PHY comes out of reset after a delay of No MORE Than 300 S. System designers should consider
this as a minimum value. After threshold
before accessing the MDIO port.
Figure 40. RESET Pulse Width and Recovery Timing
RESET
MDIO,etc.
Table 51. RESET Pulse Width and Recovery Timing Parameters
Parameter
RESET pulse width
RESET recovery delay
1. Typical values are at 25
2. Reset recovery delay is specified as a maximum value because it refers to the PHY’s guaranteed
performance. - the PHY comes out of reset after a delay of No MORE Than 300 S. System designers
should consider this as a minimum value. After de-asserting RESET, the MAC should delay No LESS than
300 S before accessing the MDIO port.
86
v
1
Sym
Min
Typ
v1
2.9
t1
o
C and are for design aid only; not guaranteed and not subject to producing testing.
1 is reached, the MAC should delay No LESS than 300 S
V
1
Sym
Min
Typ
t1
10
2
t2
o
C and are for design aid only; not guaranteed and not subject to producing testing.
t
Max
Units
Test Conditions
V
300
s
1
t
2
t
Max
Units
Test Conditions
s
300
s
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002