SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Page 66/88

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LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Table 22. Auto-Negotiation Link Partner Base Page Ability Register (Address 5)
Bit
Name
5.15
Next Page
5.14
Acknowledge
5.13
Remote Fault
5.12
Reserved
5.12:11
Asymmetric Pause
5.10
Pause
5.9
100BASE-T4
100BASE-TX
5.8
Full-Duplex
5.7
100BASE-TX
10BASE-T
5.6
Full-Duplex
5.5
10BASE-T
Selector Field
5.4:0
S[4:0]
1. Refer to
Table 16 on page 61
NOTE: Per IEEE revised standard November 1997, this register is no longer used to store Link Partner Next
Pages. Register 8 is now used for this purpose.
66
Description
1 = Link Partner has ability to send multiple pages.
0 = Link Partner has no ability to send multiple
pages.
1 = Link Partner has received Link Code Word
from LXT973.
0 = Link Partner has not received Link Code Word
from LXT973.
1 = Remote fault.
0 = No remote fault.
Write as 0, ignore on read.
Pause operation defined in IEEE 802.3, Clauses
40 and 27
Pause operation defined as of IEEE 802.3x
1 = Link Partner is 100BASE-T4 capable.
0 = Link Partner is not 100BASE-T4 capable.
1 = Link Partner is 100BASE-TX full-duplex
capable.
0 = Link Partner is not 100BASE-TX full-duplex
capable.
1 = Link Partner is 100BASE-TX capable.
0 = Link Partner is not 100BASE-TX capable.
1 = Link Partner is 10BASE-T full-duplex capable.
0 = Link Partner is not 10BASE-T full-duplex
capable.
1 = Link Partner is 10BASE-T capable.
0 = Link Partner is not 10BASE-T capable.
<00001> = IEEE 802.3
<00010> = IEEE 802.9 ISLAN-16T
<00000> = Reserved for future auto-negotiation
development
<11111> = Reserved for future auto-negotiation
development
Unspecified or reserved combinations shall not be
transmitted.
for Register Bit Descriptions.
1
Type
Default
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
00000
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002