SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 14

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SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
14
Table 1.
LXT973 PQFP Pin List (Continued)
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output,
Pin
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
OD = Open Drain output, ST = Schmitt Triggered input,
TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-down.
RXCLK0
RXER0
TXER0
TXCLK0
TXEN0
TXD0_0
VCCD
GNDD
TXD0_1
TXD0_2
TXD0_3
COL0
CRS0
VCCIO
GNDIO
LED0_1
LED0_2
LED0_3
ADDR4
ADDR3
ADDR2
ADDR1
TEST_0
TEST_1
VCCR
DPAP_0
DPAN_0
GNDT
GNDR
DPBP_0
DPBN_0
VCCT
VCCT
DPBP_1
Signal Names
AI/AO, SL
AI/AO, SL
AI/AO, SL
AI/AO, SL
AI/AO, SL
O, OD
O, OD
O, OD
Type
O, TS
O, TS
O, TS
O, TS
O, TS
I
I
I
I
I
I
I
I
I
I
I
I
1
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 6 on page 20
Table 6 on page 20
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 2 on page 16
Table 6 on page 20
Table 6 on page 20
Table 7 on page 20
Table 7 on page 20
Table 7 on page 20
Table 5 on page 19
Table 5 on page 19
Table 5 on page 19
Table 5 on page 19
Table 5 on page 19
Table 5 on page 19
Table 6 on page 20
Table 4 on page 18
Table 4 on page 18
Table 6 on page 20
Table 6 on page 20
Table 4 on page 18
Table 4 on page 18
Table 6 on page 20
Table 6 on page 20
Table 4 on page 18
Reference for Full
Description
Rev. Date: March 1, 2002
Document #: 249426
Revision #: 002
Datasheet

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