SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Page 14/88

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LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Table 1.
LXT973 PQFP Pin List (Continued)
Pin
Signal Names
34
RXCLK0
35
RXER0
36
TXER0
37
TXCLK0
38
TXEN0
39
TXD0_0
40
VCCD
41
GNDD
42
TXD0_1
43
TXD0_2
44
TXD0_3
45
COL0
46
CRS0
47
VCCIO
48
GNDIO
49
LED0_1
50
LED0_2
51
LED0_3
52
ADDR4
53
ADDR3
54
ADDR2
55
ADDR1
56
TEST_0
57
TEST_1
58
VCCR
59
DPAP_0
60
DPAN_0
61
GNDT
62
GNDR
63
DPBP_0
64
DPBN_0
65
VCCT
66
VCCT
67
DPBP_1
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output,
OD = Open Drain output, ST = Schmitt Triggered input,
TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-down.
14
Reference for Full
1
Type
Description
O, TS
Table 2 on page 16
O, TS
Table 2 on page 16
I
Table 2 on page 16
O, TS
Table 2 on page 16
I
Table 2 on page 16
I
Table 2 on page 16
Table 6 on page 20
Table 6 on page 20
I
Table 2 on page 16
I
Table 2 on page 16
I
Table 2 on page 16
O, TS
Table 2 on page 16
O, TS
Table 2 on page 16
Table 6 on page 20
Table 6 on page 20
O, OD
Table 7 on page 20
O, OD
Table 7 on page 20
O, OD
Table 7 on page 20
I
Table 5 on page 19
I
Table 5 on page 19
I
Table 5 on page 19
I
Table 5 on page 19
I
Table 5 on page 19
I
Table 5 on page 19
Table 6 on page 20
AI/AO, SL
Table 4 on page 18
AI/AO, SL
Table 4 on page 18
Table 6 on page 20
Table 6 on page 20
AI/AO, SL
Table 4 on page 18
AI/AO, SL
Table 4 on page 18
Table 6 on page 20
Table 6 on page 20
AI/AO, SL
Table 4 on page 18
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002