SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Page 47/88

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4.3
Initialization
At power-up or reset, the LXT973 performs the initialization as shown in
When the MDDISn pin is High, the LXT973 enters Manual Control Mode for that port. When
MDDISn is Low, MDIO Control Mode is enabled for that port. Mode control selection is provided
via the MDDISn pin as shown in
4.4
MDIO Control Mode
In the MDIO Control mode, the LXT973 uses the Hardware Control Interface to set up initial
(default) values of the MDIO registers. Once initial values are set, bit control reverts to the MDIO
interface.
4.5
Manual Control Mode
In the Manual Control Mode, LXT973 disables direct write operations to the MDIO registers on
the MDIO interface. The Hardware Control Interface is monitored during Reset to set up the MDIO
registers.
Figure 16. LXT973 Initialization Sequence
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Table 12 on page
48.
Power-up or Reset
Read H/W Control
Interface
Initialize MDIO
Registers
MDIO Control Mode
Manual Control Mode
MDDISn = 0
MDDIS
Pass Control to
MDIO Interface
Figure 16 on page
47.
MDDISn = 1
Disable MDIO
Writes
47