SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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If the LXT973 detects a signal fault condition, it transmits the Far End Fault Indication (FEFI) over
the fiber link. The FEFI consists of 84 consecutive “1s” followed by a single “0.” This pattern must
be repeated at least three times. The LXT973 transmits the Far-End Fault code a minimum of three
times if all the following conditions are true:
Fiber mode is selected.
Far End Fault Code transmission is enabled (Register bit 16.2 = 1).
Signal Detect indicates either no signal or the receive PLL cannot lock.
Loopback is not enabled.
3.8
100 Mbps Operation
3.8.1
100BASE-X Network Operations
During 100BASE-X operation, the LXT973 transmits and receives 5-bit symbols across the
network link.
Figure 9
actively transmitting data, the LXT973 sends out IDLE symbols on the line.
In 100BASE-TX mode, the device scrambles the data and transmits it to the network using MLT-3
line code. The MLT-3 signals received from the network are de-scrambled and decoded, and sent
across the MII to the MAC.
In 100BASE-FX mode, the LXT973 transmits and receives NRZI signals across the PECL
interface. An external 100BASE-FX transceiver module is required to complete the fiber
connection.
As shown in
Figure
9, the MAC starts each transmission with a preamble pattern. As soon as the
LXT973 detects the start of preamble, it transmits a J/K Start-of-Stream Delimiter (SSD) symbol to
the network. It then encodes and transmits the rest of the packet, including the balance of the
preamble, the Start-of-Frame Delimiter (SFD), packet data, and CRC. Once the packet ends, the
LXT973 transmits the T/R End-of-Stream Delimiter (ESD) symbol and returns to transmitting
IDLE symbols.
Figure 9. 100BASE-X Frame Format
64-Bit Preamble
(8 Octets)
P0
P1
P6
SFD
Replaced by
Start-of-Frame
/J/K/ code-groups
Delimiter (SFD)
Start-of-Stream
Delimiter (SSD)
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
shows the structure of a standard frame packet. When the MAC is not
Destination and Source
Packet Length
Data Field
Address (6 Octets each)
(2 Octets)
(Pad to minimum packet size)
DA
DA
SA
SA
L1
L2
D0
Frame Check Field
InterFrame Gap / Idle Code
(4 Octets)
(> 12 Octets)
CRC
IFG
D1
Dn
I0
Replaced by
/T/R/ code-groups
End-of-Stream Delimiter (ESD)
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