SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Tables
1
LXT973 PQFP Pin List ........................................................................................13
2
LXT973 Port 0 Signal Descriptions .....................................................................16
3
LXT973 Port 1 Signal Descriptions .....................................................................17
4
LXT973 Network Interface Signal Descriptions...................................................18
5
LXT973 Global Control & Configuration Signal Descriptions ..............................19
6
LXT973 Power Supply Signal Descriptions.........................................................20
7
LXT973 Per Port LED and Configuration Signal Descriptions ............................20
8
Carrier Sense, Loopback, and Collision Conditions ............................................26
9
Configuration Settings (Hardware Control Interface) ..........................................31
10
LED Configurations .............................................................................................40
11
Magnetics Requirements.....................................................................................43
12
Mode Control Settings.........................................................................................48
13
Configuration Settings (Hardware Control Interface) ..........................................49
14
Next Page Code Word Definitions.......................................................................51
15
Common Register Set .........................................................................................61
16
Register Bit Descriptions .....................................................................................61
17
Control Register (Address 0)...............................................................................62
18
Status Register (Address 1) ................................................................................63
19
PHY Identification Register 1 (Address 2)...........................................................64
20
PHY Identification Register 2 (Address 3)...........................................................64
21
Auto-Negotiation Advertisement Register (Address 4)........................................65
22
Auto-Negotiation Link Partner Base Page Ability Register (Address 5) ..............66
23
Auto-Negotiation Expansion Register (Address 6)..............................................67
24
Auto-Negotiation Next Page Transmit Register (Address 7)...............................67
25
Auto-Negotiation Link Partner Next Page Ability Register (Address 8)...............68
26
Port Configuration Register (Address 16) ...........................................................68
27
Special Function Register (Address 27)..............................................................70
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Magnetics Requirements.....................................................................................71
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Absolute Maximum Ratings.................................................................................72
30
Operating Conditions...........................................................................................72
31
Digital Input/Output Characteristics2...................................................................73
32
Digital Input/Output Characteristics - MII Pins.....................................................73
33
REFCLK Characteristics .....................................................................................74
34
LED Pin Characteristics ......................................................................................74
35
100BASE-TX Transceiver Characteristics ..........................................................74
36
10BASE-T Transceiver Characteristics...............................................................75
37
100BASE-FX Transceiver Characteristics ..........................................................75
38
10BASE-T Link Integrity Timing Characteristics .................................................75
39
Twisted-Pair Pins ................................................................................................76
40
MII - 100BASE-TX Transmit Timing Parameters - 4B Mode...............................77
41
MII - 100BASE-TX Receive Timing Parameters - 4B Mode................................78
42
100BASE-FX Transmit Timing Parameters.........................................................79
43
100BASE-FX Receive Timing Parameters..........................................................80
44
MII - 10BASE-T Transmit Timing Parameters (Parallel Mode) ...........................81
45
MII - 10BASE-T Receive Timing Parameters (Parallel Mode) ............................82
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10BASE-T SQE (Heartbeat) Timing Parameters ................................................83
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10BASE-T Jab and Unjab Timing Parameters....................................................83
48
Fast Link Pulse Timing Parameters ....................................................................84
49
MDIO Timing Parameters....................................................................................85
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
Contents
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