SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 21

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SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
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Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
Table 7. LXT973 Per Port LED and Configuration Signal Descriptions (Continued)
8
7
10
9
18
17
24
21
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
Pin #
ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
SD_2P5V/SPEED0
SD_2P5V/SPEED1
DUPLEX0
DUPLEX1
FIBER_TP0
FIBER_TP1
PWRDWN0
PWRDWN1
Signal Names
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Type
I
I
I
I
I
I
I
1
SD_2P5V. In fiber mode, these pins select between a 2.5V or 3.3V
fiber transceiver. High is for 2.5V and low is for 3.3V.
Speed. Set the default speed of the port in Hardware mode. High
is 100 Mbps and Low is 10 Mbps.
Duplex. Sets the duplex setting of the port in Hardware mode.
High is full-duplex and Low is half-duplex.
Fiber/Twisted-Pair. Sets the operating state of the port in
Hardware mode. High is twisted-pair and Low is fiber.
Power-Down. When set High, this pin puts the relevant PHY into
power-down mode.
Signal Description
21

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