SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Table 7. LXT973 Per Port LED and Configuration Signal Descriptions (Continued)
Pin #
Signal Names
8
SD_2P5V/SPEED0
7
SD_2P5V/SPEED1
10
DUPLEX0
9
DUPLEX1
18
FIBER_TP0
17
FIBER_TP1
24
PWRDWN0
21
PWRDWN1
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
1
Type
Signal Description
SD_2P5V. In fiber mode, these pins select between a 2.5V or 3.3V
I
fiber transceiver. High is for 2.5V and low is for 3.3V.
I
Speed. Set the default speed of the port in Hardware mode. High
is 100 Mbps and Low is 10 Mbps.
I
Duplex. Sets the duplex setting of the port in Hardware mode.
High is full-duplex and Low is half-duplex.
I
I
Fiber/Twisted-Pair. Sets the operating state of the port in
Hardware mode. High is twisted-pair and Low is fiber.
I
Power-Down. When set High, this pin puts the relevant PHY into
I
power-down mode.
21