SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Table 4. LXT973 Network Interface Signal Descriptions (Continued)
Signal
Pin #
Names
67
DPBP_1
TX+
68
DPBN_1
TX-
71
DPAP_1
RX+
72
DPAN_1
RX-
75
SD1
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
Table 5. LXT973 Global Control & Configuration Signal Descriptions
Signal
Pin #
Names
78
TxSLEW0
79
TxSLEW1
13
RESET
52
ADDR4
53
ADDR3
54
ADDR2
55
ADDR1
56
TEST_0
57
TEST_1
15
REFCLK
11
LED_CFG0
12
LED_CFG1
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
TP
Fiber
Pair
1
Port
Type
Op
Op
Type
Twisted-Pair/Fiber Pair B, Positive &
Negative - Port 1. Differential pair produces
1
B
TX-
AI/AO,
or receives IEEE 802.3-compliant pulses for
TX+
SL
1
B
either 100BASE-TX or 10BASE-T.
Also acts as transmitter in Fiber mode.
Twisted-Pair/Fiber Pair A, Positive &
Negative - Port 1. Differential pair produces
RX-
1
A
AI/AO,
or receives IEEE 802.3-compliant pulses for
SL
RX+
1
A
either 100BASE-TX or 10BASE-T.
Also acts as receiver in Fiber mode.
Signal Detect. This signal is used for signal
-
-
-
-
I
quality indication in Fiber mode. In twisted-
pair mode, this pin should be tied Low.
1
Type
Signal Description
Tx Output Slew Controls 0 & 1. These pins select the TX output slew rate
(rise and fall time) for both cores in the LXT973 device.
I
The various options are defined in Register bits 27.11:10. The TxSLEW pins set
the power-on value of these register bits.
I
Reset. This active Low input is OR’d with Control Register bit 0.15.
Address <4:1>. Sets device Port 0 PHY address. Note that ADDR0 is set
I
internally so that Port 1 is always “1” address higher than Port 0.
I
Test Pins. Tie Low for normal operation.
Master Clock Input. A 25 MHz, 50 ppm clock is input here to act as the master
clock. Full clock requirements are detailed in the Clock Requirements section of
I
the Functional Description. See
Section 3.4.2, “Clock Requirements” on
page
28.
LED Configuration 0 & 1. These pins are used to select one of four LED
modes. The decode or each mode is shown below:
LED_CFG0
LED_CFG1
LEDn_1
I
0
0
Speed
1
0
Speed
0
1
Link
1
1
Speed
Signal Description
LEDn_2
LEDn_3
Link
Duplex
Link/Activity
Duplex/Collision
Receive
Transmit
Link/MII Isolate
Duplex/Collision
19