SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 80

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SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
80
Figure 30. 100BASE-FX Receive Timing
Table 43. 100BASE-FX Receive Timing Parameters
RXD<3:0>, RXDV, RXER setup to
RXCLK High
RXD<3:0>, RXDV, RXER hold
from RXCLK High
CRS asserted to RXD<3:0>, RXDV
Receive start o “J” to CRS asserted
Receive start of “T” to CRS de-
asserted
Receive start of “J” to COL
asserted
Receive start of “T” to COL de-
asserted
1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to
production testing.
Parameter
RXD<3:0>
DPAP/N
RXCLK
RXDV
CRS
COL
0ns
Sym
t1
t2
t3
t4
t5
t6
t7
t4
t6
Min
10
10
13
10
13
3
9
t3
Typ
1
250ns
t5
t7
Max
t1
14
17
14
18
5
t2
Units
BT
BT
BT
BT
BT
ns
ns
Rev. Date: March 1, 2002
Document #: 249426
Conditions
Revision #: 002
Datasheet
Test

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