SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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3.3.4
Carrier Sense
Carrier Sense (CRS) is an asynchronous output. CRS is generated when a packet is received from
the line regardless of duplex mode, and for a transmission to the line in half-duplex mode.
on page 26
summarizes the conditions for assertion of carrier sense, collision, and data loopback
signals. Carrier sense is not generated when a packet is transmitted in full-duplex mode.
For 100BASE-TX and 100BASE-FX links, a Start-of-Stream Delimiter (SSD) or /J/K/ symbol pair
causes assertion of carrier sense (CRS). An End-of-Stream Delimiter (ESD), or /T/R/ symbol pair
causes de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received
without /T/R/. In this event, the RXER bit in the RX Status Frame is asserted for one clock cycle
when CRS is de-asserted.
For 10BASE-T links, CRS assertion is based on receipt of a valid preamble, and de-assertion is
based on receipt of an End-of-Frame (EOF) marker.
3.3.5
Error Signals
When the LXT973 is in 100 Mbps mode and receives an invalid symbol from the network, it
asserts RXER and drives “1110” on the RXD pins.
When the MAC asserts TXER, the LXT973 drives “H” symbols out on the DPAP/N_0 or
DPAP/N_1 pins.
3.3.6
Collision
The LXT973 asserts its collision signal, asynchronously to any clock, when the line state is half-
duplex and the transmitter and receiver are active at the same time.
the conditions for assertion of carrier sense, collision, and data loopback signals.
3.3.7
Loopback
The LXT973 provides two loopback functions, operational and test (see
Loopback paths are shown in
3.3.7.1
Operational Loopback
Operational loopback is provided for 10 Mbps half-duplex links when Register bit 16.8 = 0. Data
transmitted by the MAC (TXD) is looped back on the receive side of the MII (RXD). Operational
loopback is not provided for 100 Mbps links, full-duplex links, or when Register bit 16.8 = 1.
3.3.7.2
Test Loopback
A test loopback function is provided for diagnostic testing of the LXT973. During test loopback,
twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally looped
back by the LXT973 and returned to the MAC.
Test loopback is available for both 100BASE-TX and 10BASE-T operation. Test loopback is
enabled by setting the register bits as follows:
Register bit 0.14 = 1 (loopback mode)
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Figure 4 on page
26.
Table 8
Table 8 on page 26
summarizes
Table 8 on page
26).
25