SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
3.0
Functional Description
3.1
Introduction
The LXT973 is an IEEE-compliant, dual-port, Fast Ethernet PHY transceiver that directly supports
both 100BASE-TX and 10BASE-T applications. The device incorporates full Media Independent
Interface (MII), enabling each individual network port to connect with 10/100 Mbps MACs. Each
port directly drives either a 100BASE-TX line or a 10BASE-T line (up to 160 meters). The
LXT973 also supports 100BASE-FX operation via a Pseudo-ECL (PECL) interface. The device
uses a 100-pin QFP package.
3.1.1
Comprehensive Functionality
The LXT973 performs all functions of the Physical Coding Sublayer (PCS) and Physical Media
Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X specification. This device
also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX
connections.
On power-up, the LXT973 reads its configuration inputs to check for forced operation settings. If
not configured for forced operation, each port uses auto-negotiation/parallel detection to
automatically determine line operating conditions. If the link partner supports auto-negotiation, the
LXT973 auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not
support auto-negotiation, the LXT973 automatically detects (parallel detection) the presence of
either link pulses (10 Mbps PHY) or IDLE symbols (100 Mbps PHY) and sets its operating
conditions accordingly. When parallel detection is used to establish link, the resulting link is at
half-duplex. The LXT973 provides half-duplex and full-duplex operation at 100 Mbps and 10
Mbps.
3.2
Interface Descriptions
3.2.1
10/100 Mbps Network Interface
The LXT973 supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or 100 Mbps
Ethernet over fiber media (100BASE-FX). Each network interface port consists of four external
pins (two differential signal pairs). The pins are shared between twisted-pair and fiber.
The LXT973 output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX output.
When not transmitting data, the device generates IEEE 802.3-compliant link pulses or IDLE code.
Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input, depending
on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine
the speed of this interface. Polarity is determined by the MDI crossover function.
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Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002