SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Table 24. Auto-Negotiation Next Page Transmit Register (Address 7) (Continued)
Bit
Name
Acknowledge 2
7.12
(ACK2)
Toggle
7.11
(T)
Message/Unformatted
7.10:0
Code Field
1. Refer to
Table 16 on page 61
Table 25. Auto-Negotiation Link Partner Next Page Ability Register (Address 8)
Bit
Name
Next Page
8.15
(NP)
Acknowledge
8.14
(ACK)
Message Page
8.13
(MP)
Acknowledge 2
8.12
(ACK2)
Toggle
8.11
(T)
Message/
8.10:0
Unformatted Code
Field
1. Refer to
Table 16 on page 61
Table 26. Port Configuration Register (Address 16)
Bit
Name
16.15
Reserved
16.14
Link Test Disable
16.13
Transmit Disable
1. Refer to
Table 16 on page 61
2. Register bit 16.0 is latched in from hardware pins on hardware reset.
68
Description
1 = Complies with message
0 = Does not comply with message
1 = Previous value of the transmitted Link Code
Word was equal to logic zero
0 = Previous value of the transmitted Link Code
Word was equal to logic one
See Appendix C of the IEEE 802.3 standards for
Next Page descriptions
for Register Bit Descriptions.
Description
1 = Link Partner has additional Next Pages to send
0 = Link Partner has no additional Next Pages to
send
1 = Link Partner has received Link Code Word from
LXT973
0 = Link Partner has not received Link Code Word
from LXT973
1 = Page sent by the Link Partner is a Message
Page
0 = Page sent by the Link Partner is an
Unformatted Page
1 = Link Partner complies with the message
0 = Link Partner cannot comply with the message
1 = Previous value of the transmitted Link Code
Word was equal to logic zero
0 = Previous value of the transmitted Link Code
Word equalled logic one
See Appendix C of the IEEE 802.3 standards for
Next Page descriptions
for Register Bit Descriptions.
Description
Write as 0, ignore on read
1 = Force Link pass (sets appropriate registers
and LEDs to pass)
0 = Normal operation
1 = Disable twisted-pair transmitter
0 = Normal operation
for Register Bit Descriptions.
1
Type
Default
R/W
0
R/W
0
00000000
R/W
001
1
Type
Default
RO
0
RO
0
RO
0
RO
0
RO
0
00000000
RO
000
1
Type
Default
R/W
0
R/W
0
R/W
0
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002