SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Table 23. Auto-Negotiation Expansion Register (Address 6)
Bit
Name
6.15:6
Reserved
6.5
Base Page
Parallel Detection
6.4
Fault
Link Partner Next
6.3
Page Able
6.2
Next Page Able
6.1
Page Received
Link Partner Auto-
6.0
Neg Able
1. Refer to
Table 16 on page 61
2. Bits that Latch High (LH) or Latch Low (LL) automatically clear when read.
NOTE: This table contains modifications that are selectable in Intel PHYs. These modifications are used to
ease the implementation of software Next Page. See separate Intel tutorial/white-paper on the usage
of Next Pages.
Table 24. Auto-Negotiation Next Page Transmit Register (Address 7)
Bit
Name
Next Page
7.15
(NP)
7.14
Reserved
Message Page
7.13
(MP)
1. Refer to
Table 16 on page 61
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Description
Write as 0, ignore on read
This bit indicates the status of the auto-negotiation
variable, Base Page. It also flags synchronization
with the auto-negotiation state diagram, allowing
detection of interrupted links. This bit is only used if
Register bit 16.1 (Alternate Next Page feature) is
set.
1 = base_page = true
0 = base_page = false
1 = Parallel Detection Fault has occurred.
0 = Parallel Detection Fault has not occurred.
1 = Link partner is Next Page able.
0 = Link partner is not Next Page able.
1 = Local device is Next Page able
0 = Local device is not Next Page able
Indicates that a new page has been received and
the received code word has been loaded into
Register 5 (Base Pages) or Register 8 (Next
Pages) as specified in clause 28 of IEEE 802.3.
This bit is cleared on read. If Register bit 16.1 is set,
the Page Received bit is also cleared when
mr_page_rx = false, or transmit_disable = true.
1 = Link partner is auto-negotiation able.
0 = Link partner is not auto-negotiation able.
for Register Bit Descriptions.
Description
1 = Additional Next Pages follow
0 = Last page
Write as 0, ignore on read
1 = Message Page
0 = Unformatted page
for Register Bit Descriptions.
1
Type
Default
RO
0
RO/LH
0
Note 2
RO/LH
0
Note 2
RO
0
RO
1
RO/LH
0
Note 2
RO
0
1
Type
Default
R/W
0
RO
0
R/W
1
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