SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 15

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SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
Table 1. LXT973 PQFP Pin List (Continued)
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output,
100
Pin
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
OD = Open Drain output, ST = Schmitt Triggered input,
TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-down.
DPBN_1
GNDR
GNDT
DPAP_1
DPAN_1
VCCR
VCCPECL
SD1
SD0
GNDPECL
TxSLEW0
TxSLEW1
LED1_3
LED1_2
LED1_1
GNDIO
VCCIO
RXD1_3
RXD1_2
RXD1_1
RXD1_0
RXDV1
GNDD
VCCD
RXCLK1
RXER1
TXER1
GNDIO
VCCIO
TXCLK1
TXEN1
TXD1_0
TXD1_1
Signal Names
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
AI/AO, SL
AI/AO, SL
AI/AO, SL
O. OD
O, OD
O, OD
Type
O, TS
O, TS
O, TS
O, TS
O, TS
O, TS
O, TS
O, TS
I
I
I
I
I
I
I
I
1
Table 4 on page 18
Table 6 on page 20
Table 6 on page 20
Table 4 on page 18
Table 4 on page 18
Table 6 on page 20
Table 6 on page 20
Table 4 on page 18
Table 4 on page 18
Table 6 on page 20
Table 5 on page 19
Table 5 on page 19
Table 7 on page 20
Table 7 on page 20
Table 7 on page 20
Table 6 on page 20
Table 6 on page 20
Table 3 on page 17
Table 3 on page 17
Table 3 on page 17
Table 3 on page 17
Table 3 on page 17
Table 6 on page 20
Table 3 on page 17
Table 3 on page 17
Table 3 on page 17
Table 6 on page 20
Table 6 on page 20
Table 3 on page 17
Table 3 on page 17
Table 3 on page 17
Table 3 on page 17
Table 3 on page 17
Reference for Full
Description
15

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