SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Table 1. LXT973 PQFP Pin List (Continued)
Pin
Signal Names
68
DPBN_1
69
GNDR
70
GNDT
71
DPAP_1
72
DPAN_1
73
VCCR
74
VCCPECL
75
SD1
76
SD0
77
GNDPECL
78
TxSLEW0
79
TxSLEW1
80
LED1_3
81
LED1_2
82
LED1_1
83
GNDIO
84
VCCIO
85
RXD1_3
86
RXD1_2
87
RXD1_1
88
RXD1_0
89
RXDV1
90
GNDD
91
VCCD
92
RXCLK1
93
RXER1
94
TXER1
95
GNDIO
96
VCCIO
97
TXCLK1
98
TXEN1
99
TXD1_0
100
TXD1_1
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output,
OD = Open Drain output, ST = Schmitt Triggered input,
TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-down.
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Reference for Full
1
Type
Description
AI/AO, SL
Table 4 on page 18
Table 6 on page 20
Table 6 on page 20
AI/AO, SL
Table 4 on page 18
AI/AO, SL
Table 4 on page 18
Table 6 on page 20
Table 6 on page 20
I
Table 4 on page 18
I
Table 4 on page 18
Table 6 on page 20
I
Table 5 on page 19
I
Table 5 on page 19
O. OD
Table 7 on page 20
O, OD
Table 7 on page 20
O, OD
Table 7 on page 20
Table 6 on page 20
Table 6 on page 20
O, TS
Table 3 on page 17
O, TS
Table 3 on page 17
O, TS
Table 3 on page 17
O, TS
Table 3 on page 17
O, TS
Table 3 on page 17
Table 6 on page 20
Table 3 on page 17
O, TS
Table 3 on page 17
O, TS
Table 3 on page 17
I
Table 6 on page 20
Table 6 on page 20
Table 3 on page 17
O, TS
Table 3 on page 17
I
Table 3 on page 17
I
Table 3 on page 17
I
Table 3 on page 17
15