SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 26

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SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Register bit 0.8 = 1 (full-duplex)
Register bit 0.12 = 0 (disable auto-negotiation).
Figure 4. Loopback Paths
LXT973
MII
Loopback
Table 8.
Carrier Sense, Loopback, and Collision Conditions
Speed
Duplex Condition
Full-Duplex
Full-Duplex
100 Mbps
Half-Duplex
Full-Duplex
Full-Duplex
Half-Duplex,
10 Mbps
Register bit 16.8 = 0
Half-Duplex,
Register bit 16.8 = 1
1. Test Loopback is enabled when Register bits 0.14 = 1, 0.8 = 1, and 0.12 = 0.
3.3.8
Configuration Management Interface
The LXT973 provides an MDIO Management Interface and a Hardware Control Interface for
device configuration and management.
3.3.8.1
MII Management Interface
The LXT973 supports the IEEE 802.3 MII Management Interface also known as the Management
Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and
control the state of the LXT973. The MDIO interface consists of a physical connection, a specific
protocol which runs across the connection, and an internal set of addressable registers. The
physical interface consists of a data line (MDIO) and clock line (MDC), and a control line
(MDDIS). The maximum speed of MDC is 20 MHz.
26
10T
Digital
100X
Analog
Block
Loopback
Block
Test
Carrier Sense
Loopback
Receive Only
Yes
Receive Only
No
Transmit or Receive
No
Receive Only
Yes
Receive Only
No
Transmit or Receive
Yes
Transmit or Receive
No
FX
Driver
TX
Driver
1
Operational
Collision
Loopback
No
None
No
None
Transmit and
No
Receive
No
None
No
None
Transmit and
Yes
Receive
Transmit and
No
Receive
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002

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