SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Table 26. Port Configuration Register (Address 16) (Continued)
Bit
Name
Bypass Scramble
16.12
(100BASE-TX)
Bypass 4B/5B
16.11
(100BASE-TX)
Jabber
16.10
(10BASE-T)
SQE
16.9
(10BASE-T)
TP Loopback
16.8
(10BASE-T)
CRS Select
16.7
(10BASE-T)
16.6
Reserved
16.5
PRE_EN
16.4
Reserved
16.3
10M Serial
Far End Fault
16.2
Transmission Enable
16.1
Alternate NP Feature
16.0
Fiber Select
1. Refer to
Table 16 on page 61
2. Register bit 16.0 is latched in from hardware pins on hardware reset.
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Description
1 = Bypass Scrambler and De-scrambler
0 = Normal operation
1 = Bypass 4B/5B encoder and decoder
0 = Normal Operation
1 = Disable Jabber
0 = Normal operation
1 = Enable Heart Beat
0 = Disable Heart Beat
1 = Disable twisted-pair loopback during half-
duplex operation
0 = Normal Operation - loopback in 10BASE-T,
half-duplex
1 = CRS de-assert extends to RXDV de-assert
0 = Normal operation
Write as 0, ignore on read
Preamble Enable.
0 = Set RXDV High coincident with SFD
1 = Set RXDV High and RXD = preamble when
CRS is asserted.
Write as 0, ignore on read
1 = 10BASE_T serial mode. 10 Mbps data is
driven serially on RXD<0> in this mode.
0 = Utilize normal MII mode-nibble.
1 = Enable Far End Fault transmission.
0 = Disable Far End Fault transmission.
1 = Enable Alternate auto-negotiation Next
Page feature.
0 = Disable Alternate auto-negotiation Next
Page feature.
1 = Select fiber mode for this port.
0 = Select twisted-pair mode for this port.
for Register Bit Descriptions.
1
Type
Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
LHR
R/W
Note 2
69