SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Page 82/88

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LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Figure 32. 10BASE-T Receive Timing (Parallel Mode)
RXCLK
RXD,
RXDV,
RXER
CRS
Twisted-Pair
Input
COL
NOTE: Twisted-pair input default pins are as follows: DPBP/N_0 and DPAP/N_1.
Table 45. MII - 10BASE-T Receive Timing Parameters (Parallel Mode)
Parameter
RXD, RXDV, RXER setup to
RXCLK High
RXD, RXDV, RXER hold from
RXCLK High
Twisted-pair input to RXD out (Rx
latency)
CRS asserted to RXD, RXDV,
2
RXER asserted
RXD, RXDV, RXER de-asserted
3
to CRS de-asserted
Twisted-pair input to CRS
asserted
Twisted-pair input quiet to CRS
de-asserted
Twisted-pair input to COL
asserted
Twisted-pair input quiet to COL
de-asserted
1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. CRS is asserted. RXD/RXDV are driven at the start of SFD (64 BT) unless Register bit 16.5 is set.
3. If Register bit 16.7 is set, CRS extends to RXDV de-assert.
82
t
t
1
2
t
3
t
4
t
6
t
8
1
Sym
Min
Typ
t1
10
t2
10
t3
64
t4
62
t5
0.5
t6
4
t7
4
t8
4
t9
4
t
5
t
7
t
9
Max
Units
Test Conditions
ns
ns
BT
BT
BT
BT
BT
BT
BT
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002