SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 82

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SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
82
Figure 32. 10BASE-T Receive Timing (Parallel Mode)
Table 45. MII - 10BASE-T Receive Timing Parameters (Parallel Mode)
RXD, RXDV, RXER setup to
RXCLK High
RXD, RXDV, RXER hold from
RXCLK High
Twisted-pair input to RXD out (Rx
latency)
CRS asserted to RXD, RXDV,
RXER asserted
RXD, RXDV, RXER de-asserted
to CRS de-asserted
Twisted-pair input to CRS
asserted
Twisted-pair input quiet to CRS
de-asserted
Twisted-pair input to COL
asserted
Twisted-pair input quiet to COL
de-asserted
NOTE: Twisted-pair input default pins are as follows: DPBP/N_0 and DPAP/N_1.
1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to
2. CRS is asserted. RXD/RXDV are driven at the start of SFD (64 BT) unless Register bit 16.5 is set.
3. If Register bit 16.7 is set, CRS extends to RXDV de-assert.
Twisted-Pair
production testing.
RXCLK
RXDV,
RXER
RXD,
Input
CRS
COL
Parameter
2
3
t
6
t
8
t
Sym
3
t1
t2
t3
t4
t5
t6
t7
t8
t9
t
4
Min
10
10
Typ
t
1
0.5
64
62
4
4
4
4
1
t
2
Max
Units
BT
BT
BT
BT
BT
BT
BT
ns
ns
t
t
7
9
Rev. Date: March 1, 2002
Document #: 249426
Test Conditions
t
5
Revision #: 002
Datasheet

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