SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 33

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SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
3.7
3.7.1
3.7.2
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
Figure 8. Auto-Negotiation Operation
Network Media/Protocol Support
The LXT973 supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or 100 Mbps
Ethernet over fiber media (100BASE-FX).
10/100 Mbps Network Interface
The network interface port consists of five external pins (two differential signal pairs and a signal
detect pin). The differential signal pins are shared between twisted-pair and fiber. Refer to
on page 23
The LXT973 output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX output.
When not transmitting data, the LXT973 generates IEEE 802.3-compliant link pulses or an IDLE
code. Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input,
depending on the mode selected. Auto-negotiation/parallel detection or manual control is used to
determine the speed of this interface.
Twisted-Pair Interface
When operating at 100 Mbps, the LXT973 continuously transmits and receives MLT3 symbols.
When not transmitting data, the LXT973 generates IDLE symbols.
During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being
exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link
up.
Auto-Negotiation
Go To Forced
Settings
Disable
for specific pin assignments.
Done
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
0.12 = 0
Power-Up, Reset,
Link Failure
Check Value
Start
0.12
Attempt Auto-
Negotiation
0.12 = 1
YES
Listen for 100TX
Idle Symbols
Auto-Neg/Parallel Detection
Link Set?
Enable
NO
Listen for 10T
Link Pulses
Figure 3
33

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