SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Page 27/88

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Operation of this interface is controlled by the MDDISn input pin. When MDDISn is High, the
MDIO is completely disabled. When MDDISn is Low, read and write are enabled. The timing for
the MDIO Interface is shown in
6
for write operations. The protocol allows one controller to communicate with multiple LXT973
devices. Each LXT973 port is assigned an address between 0 and 31, as described in
page 19
(ADDR<4:1>).
The LXT973 supports the core 16-bit MDIO registers. Registers 0-10 and 15 are required and their
functions are specified by the IEEE 802.3 specification. Additional registers are included for
expanded functionality. Specific bits in the registers are referenced using an “X.Y” notation, where
X is the register number (0-31) and Y is the bit number (0-15)
Figure 5. Management Interface Read Frame Structure
MDC
MDIO
0
1
1
0
32 "1"s
(Read)
Preamble
ST
Op Code
High Z
Figure 6. Management Interface Write Frame Structure
MDC
MDIO
32 "1"s
0
1
0
1
(Write)
Idle
Preamble
ST
Op Code
3.3.8.2
MII Addressing
The MDIO management protocol allows one controller to communicate with multiple LXT973
chips. Pins ADDR_<4:1> determine the base address. Each port adds its port number to the base
address to obtain its port address as shown in
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Table 49 on page
85. See
Figure 5
A4
A3
A0
R4
R3
R0
Z
Turn
PHY Address
Register Address
Around
Write
A4
A3
A0
R4
R3
R0
1
Turn
PHY Address
Register Address
Around
Write
Figure 7 on page
for read operations, and
Figure
Table 5 on
D1
D15
D14
D15
D14
D1
D0
0
Data
Idle
Read
D15
D14
D1
D0
0
Data
Idle
28.
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