SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 27

no-image

SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
3.3.8.2
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
MDIO
(Read)
MDC
(Write)
MDIO
High Z
MDC
Figure 5. Management Interface Read Frame Structure
Figure 6. Management Interface Write Frame Structure
Idle
Preamble
32 "1"s
Preamble
32 "1"s
Operation of this interface is controlled by the MDDISn input pin. When MDDISn is High, the
MDIO is completely disabled. When MDDISn is Low, read and write are enabled. The timing for
the MDIO Interface is shown in
6
devices. Each LXT973 port is assigned an address between 0 and 31, as described in
page 19
The LXT973 supports the core 16-bit MDIO registers. Registers 0-10 and 15 are required and their
functions are specified by the IEEE 802.3 specification. Additional registers are included for
expanded functionality. Specific bits in the registers are referenced using an “X.Y” notation, where
X is the register number (0-31) and Y is the bit number (0-15)
MII Addressing
The MDIO management protocol allows one controller to communicate with multiple LXT973
chips. Pins ADDR_<4:1> determine the base address. Each port adds its port number to the base
address to obtain its port address as shown in
for write operations. The protocol allows one controller to communicate with multiple LXT973
0
0
ST
ST
1
1
(ADDR<4:1>).
1
0
Op Code
Op Code
0
1
Write
A4
A4
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
PHY Address
PHY Address
A3
A3
Table 49 on page
A0
A0
Write
R4
R4
Register Address
Register Address
R3
R3
Figure 7 on page
85. See
R0
R0
Z
1
Around
Turn
Around
Figure 5
Turn
0
0
D15
28.
D15
D15
for read operations, and
D14
Data
Read
D14
D14
D1
Data
D1
D1
D0
D0
Table 5 on
Idle
Idle
Figure
27

Related parts for SLXT973QC.A2