SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Table 1. LXT973 PQFP Pin List
Pin
Signal Names
1
TXD1_2
2
TXD1_3
3
COL1
4
CRS1
5
AUTO_NEG1
6
AUTO_NEG0
7
SD_2P5V/SPEED1
8
SD_2P5V/SPEED0
9
DUPLEX1
10
DUPLEX0
11
LED_CGF0
12
LED_CGF1
13
RESET
14
SGND
15
REFCLK
16
GNDD
17
FIBER_TP1
18
FIBER_TP0
19
MDDIS1
20
MDDIS0
21
PWRDWN1
22
MDC1
23
MDIO1
24
PWRDWN0
25
MDIO0
26
MDC0
27
VCCIO
28
GNDIO
29
RXD0_3
30
RXD0_2
31
RXD0_1
32
RXD0_0
33
RXDV0
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output,
OD = Open Drain output, ST = Schmitt Triggered input,
TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-down.
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Reference for Full
1
Type
Description
I
Table 3 on page 17
I
Table 3 on page 17
O, TS
Table 3 on page 17
O, TS
Table 3 on page 17
I
Table 7 on page 20
I
Table 7 on page 20
I
Table 7 on page 20
I
Table 7 on page 20
I
Table 7 on page 20
I
Table 7 on page 20
I
Table 5 on page 19
I
Table 5 on page 19
I
Table 5 on page 19
Table 6 on page 20
I
Table 5 on page 19
Table 6 on page 20
I
Table 7 on page 20
I
Table 7 on page 20
I
Table 3 on page 17
I
Table 2 on page 16
I
Table 7 on page 20
I
Table 3 on page 17
I/O
Table 3 on page 17
I
Table 7 on page 20
I/O
Table 2 on page 16
I
Table 2 on page 16
Table 6 on page 20
Table 6 on page 20
O, TS
Table 2 on page 16
O, TS
Table 2 on page 16
O, TS
Table 2 on page 16
O, TS
Table 2 on page 16
O, TS
Table 2 on page 16
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