SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 5

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SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
A
Figures
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
Fiber Interface
10 Mbps Operation
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
Clock Generation
11.1
Register Definitions
Magnetics Information
Test Specifications
Timing Diagrams
Mechanical Specifications
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Product Ordering Information
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
Link Test..............................................................................................................57
10Base-T Link Failure Criteria and Override.......................................................57
SQE (Heartbeat)..................................................................................................57
Jabber .................................................................................................................57
Polarity Correction...............................................................................................57
Dribble Bits ..........................................................................................................58
Transmit Polarity Control.....................................................................................58
PHY Address.......................................................................................................58
External Oscillator ...............................................................................................59
LXT973 Block Diagram .......................................................................................11
LXT973 Pin Assignments ....................................................................................12
LXT973 Interfaces ..............................................................................................23
Loopback Paths ..................................................................................................26
Management Interface Read Frame Structure ...................................................27
Management Interface Write Frame Structure ...................................................27
Port Address Scheme .........................................................................................28
Auto-Negotiation Operation ................................................................................33
100BASE-X Frame Format ................................................................................35
Protocol Sublayers .............................................................................................36
Typical LED Implementation ..............................................................................40
Power and Ground Supply Connections ............................................................44
Typical Twisted-Pair Interface ............................................................................45
Typical Fiber Interface ........................................................................................46
Typical MII Interface ...........................................................................................46
LXT973 Initialization Sequence...........................................................................47
100BASE-TX Frame Format ...............................................................................53
100BASE-TX Data Path ......................................................................................53
100BASE-TX Reception with no Errors...............................................................54
100BASE-TX Reception with Invalid Symbol ......................................................55
Scrambler Seeding.................................................................................54
Scrambler Bypass ..................................................................................54
100BASE-T Link Failure Criteria and Override ......................................54
Baseline Wander Correction ..................................................................54
Programmable Tx Slew Rate .................................................................54
............................................................................................................56
......................................................................................................59
......................................................................................................77
..................................................................................................57
..................................................................................................72
.................................................................................................61
...........................................................................................71
....................................................................................87
.......................................................................88
Contents
5

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