SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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8.1.1
Scrambler Seeding.................................................................................54
8.1.2
Scrambler Bypass ..................................................................................54
8.1.3
100BASE-T Link Failure Criteria and Override ......................................54
8.1.4
Baseline Wander Correction ..................................................................54
8.1.5
Programmable Tx Slew Rate .................................................................54
9.0
Fiber Interface
............................................................................................................56
10.0
10 Mbps Operation
10.1
Link Test..............................................................................................................57
10.2
10Base-T Link Failure Criteria and Override.......................................................57
10.3
SQE (Heartbeat)..................................................................................................57
10.4
Jabber .................................................................................................................57
10.5
Polarity Correction...............................................................................................57
10.6
Dribble Bits ..........................................................................................................58
10.7
Transmit Polarity Control.....................................................................................58
10.8
PHY Address.......................................................................................................58
11.0
Clock Generation
11.1
External Oscillator ...............................................................................................59
12.0
Register Definitions
13.0
Magnetics Information
14.0
Test Specifications
15.0
Timing Diagrams
16.0
Mechanical Specifications
A
Product Ordering Information
Figures
1
LXT973 Block Diagram .......................................................................................11
2
LXT973 Pin Assignments ....................................................................................12
3
LXT973 Interfaces ..............................................................................................23
4
Loopback Paths ..................................................................................................26
5
Management Interface Read Frame Structure ...................................................27
6
Management Interface Write Frame Structure ...................................................27
7
Port Address Scheme .........................................................................................28
8
Auto-Negotiation Operation ................................................................................33
9
100BASE-X Frame Format ................................................................................35
10
Protocol Sublayers .............................................................................................36
11
Typical LED Implementation ..............................................................................40
12
Power and Ground Supply Connections ............................................................44
13
Typical Twisted-Pair Interface ............................................................................45
14
Typical Fiber Interface ........................................................................................46
15
Typical MII Interface ...........................................................................................46
16
LXT973 Initialization Sequence...........................................................................47
17
100BASE-TX Frame Format ...............................................................................53
18
100BASE-TX Data Path ......................................................................................53
19
100BASE-TX Reception with no Errors...............................................................54
20
100BASE-TX Reception with Invalid Symbol ......................................................55
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
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Contents
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