SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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5.0
Configuration
When the LXT973 is first powered on, reset, or encounters a link-down state, it must determine the
line speed and operating conditions to use for the network link. The LXT973 first checks the
MDIO registers (initialized via the Hardware Control Interface or written by software) for
operating instructions. Using these mechanisms, the user can command the LXT973 to do one of
the following:
Forced 100BASE-FX operation
Forced twisted-pair link operation to:
— 100BASE-TX, full-duplex
— 100BASE-TX, half-duplex
— 10BASE-T, full-duplex
— 10BASE-T, half-duplex
Allow auto-negotiation/parallel-detection.
In forced twisted-pair link operation, the LXT973 immediately begins operating the network
interface as commanded. In the last case, the LXT973 begins the auto-negotiation/parallel-
detection process.
Several pins are used to configure the LXT973 device.
configurations to the port. Usually these pins are decodes of chip pins. This is useful for manual
configuration.
Table 13. Configuration Settings (Hardware Control Interface)
FIBER_TPn
AUTO_NEGx
Low
-
Low
-
High
High
High
High
High
High
High
High
High
Low
1. These pins also set the default values for Registers 0 and 4 accordingly.
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Table 13
SPEEDx
DUPLEXx
100BASE-FX is enabled in half-duplex mode.
-
Low
Auto-negotiation is disabled
100BASE-FX is enabled in full-duplex mode.
-
High
Auto-negotiation is disabled.
AUTO_NEG is enabled. All capabilities are
advertised.
High
High
Register bits 4.8, 4.7, 4.6 and 4.5 are all set to 1.
AUTO_NEG is enabled. Only 100 Mbps
capabilities are advertised.
High
Low
Register bits 4.8 and 4.7are set to 1. Register bits
4.6 and 4.5 are cleared to 0.
AUTO_NEG is enabled. Only 10 Mbps capabilities
are advertised.
Low
High
Register bits 4.8 and 4.7 are cleared to 0. Register
bits 4.6 and 4.5 are set to 1.
AUTO_NEG is enabled. Only half-duplex
capabilities are advertised.
Low
Low
Register bits 4.7 and 4.5 are set 1. Register bits
4.8 and 4.6 are cleared to 0.
AUTO_NEG is disabled. LXT973 port x is forced
High
High
to 100 Mbps full-duplex operation.
summarizes the available manual
Mode
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