SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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12.0
Register Definitions
The LXT973 register set includes 16 registers per port. Refer to
listing.
Base Registers 0 through 8 are defined in accordance with the “Reconciliation Sublayer and Media
Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-Negotiation”
sections of the IEEE 802.3 specification.
Additional registers are defined in accordance with the IEEE 802.3 specification for adding unique
chip functions.
Table 15. Common Register Set
Address
0
Control Register
1
Status Register
2
PHY Identification Register 1
3
PHY Identification Register 2
4
Auto-Negotiation Advertisement Register
5
Auto-Negotiation Link Partner Base Page Ability Register Refer to
6
Auto-Negotiation Expansion Register
7
Auto-Negotiation Next Page Transmit Register
Auto-Negotiation Link Partner Received Next Page
8
Register
16
Port Configuration Register
18
Reserved
26
Reserved
27
Special Function Register
28
Reserved
29
Reserved
30
Reserved
31
Reserved
Table 16. Register Bit Descriptions
Bit Type
R/W
Read and Write capable
RO
Read Only
WO
Write Only
AC
Auto Clear on Read
LHR
Latched from external pins on reset
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Register Name
Description
Table 15
for a complete register
Bit Definitions
Refer to
Table 17 on page 62
Refer to
Table 18 on page 63
Refer to
Table 19 on page 64
Refer to
Table 20 on page 64
Refer to
Table 21 on page 65
Table 22 on page 66
Refer to
Table 23 on page 67
Refer to
Table 24 on page 67
Refer to
Table 25 on page 68
Refer to
Table 26 on page 68
Refer to
Table 27 on page 70
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