SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Page 11/88

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Figure 1. LXT973 Block Diagram
RESET
Management /
Mode Select
PWRDN
Logic & LED
Drivers
MDIO
MDC
Register Set
TXDn<3.0>
TXENn
Parallel/Serial
TXERn
Converter
TXCLKn
Mgmt
Counters
Register Set
Port LED
Drivers
3
LED <3:0>
Serial to
RXDn<3.0>
Parallel
RXDVn
Converter
RXERn
Carrier Sense
RXCLKn
Data Valid
COLn
Error Detect
CRSn
Please see
Table 4, “LXT973 Network Interface Signal Descriptions” on page 18
Global Control & Configuration Signal Descriptions” on page 19
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
2 Port Global
Functions
Clock
Generator
+
Manchester
10
TP
Encoder
Driver
Pulse
-
Scrambler
Shaper
100
& Encoder
+
ECL
Auto
Driver
CIM
Negotiation
-
Media
Clock Generator
Adaptive EQ with BL
Select
Wander Cancellation
Manchester
10
Decoder
Slicer
Decoder &
100
Descrambler
Per-Port Functions
PORT 0
PORT 1
for complete network interface signal
REFCLK
DPAN_0
TP/
Fiber
DPAP_0
Out
DPBN_1
DPBP_1
Fiber_TPn
+
100TX
DPBN_0
-
TP/
+
DPBP_0
Fiber
100FX
DPAN_1
In
-
DPAP_1
+
10BT
-
and
Table 5, “LXT973
11