SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 53

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SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
8.0
8.1
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
Figure 17. 100BASE-TX Frame Format
Figure 18. 100BASE-TX Data Path
100 Mbps Operation
The MAC passes data to the LXT973 over the MII. The LXT973 encodes and scrambles the data,
then transmits it using MLT-3 (for 100BASE-TX-over-copper), or NRZI signaling (for
100BASE-FX-over-fiber). The LXT973 descrambles and decodes MLT-3 data received from the
network. When the MAC is not actively transmitting data, the LXT973 sends out IDLE symbols on
the line.
As shown in
When TXEN is asserted, the LXT973 transmits a /J/K/ symbol to the network (Start of Stream
Delimiter or SSD). It then encodes and transmits the rest of the packet, including the balance of the
preamble, the SFD (Start of Frame Delimiter), packet data, and CRC. Once the packet ends, the
LXT973 transmits the
/T/R/symbol (End-of-Stream Delimiter (ESD)) and then returns to transmitting IDLE symbols.
The encoder translates the 4-bit nibbles into 5-bit symbols, which are sent over the 100BASE-TX
connection. A fifth bit is provided on pins TXER0 and TXER1 during symbol mode to allow a 5-
bit symbol to be sent across the MII interface. The 5B encoder is bypassed in symbol mode.
Figure 18
Displaying Symbol Errors
The PHY provides the MAC with an indication of errors that occur during the receive process. This
output is called RXER. It is possible to map the symbol error detection output to the RXER pin
using Register bit 26.9. In normal mode (Register bit 26.9 = 0), the RXER output is active per the
IEEE 802.3 standard. When this register bit = 1, the RXER output goes active only when a symbol
error is detected. This provides a quick measure of bit error rate.
Standard MII Mode Data Flow
D0
D1
D2
D3
Replaced by
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)
P0
64-Bit Preamble
P1
shows the data conversion flow from nibbles to symbols.
(8 Octets)
Parallel
Parallel
Serial
Serial
to
to
Figure 17 on page
P6
Delimiter (SFD)
Start-of-Frame
SFD
D0 D1 D2 D3
DA
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Address (6 Octets each)
Destination and Source
DA
53, the MAC starts each transmission with a preamble pattern.
SA
4B/5B
5B/4B
SA
Packet Length
L1
S0 S1
(2 Octets)
L2
S2 S3
(Pad to minimum packet size)
D0
Data Field
S4
D1
Dn
Scramble
Scramble
De-
Frame Check Field
(4 Octets)
CRC
End-of-Stream Delimiter (ESD)
MLT3
/T/R/ code-groups
Replaced by
pattern: 0, +1, 0, -1, 0, +1...
InterFrame Gap / Idle Code
All transitions must follow
0
I0
No Transition = 0.
Transition = 1.
(> 12 Octets)
+1
0
IFG
-1
53
0

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