SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Page 84/88

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LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Figure 35. Fast Link Pulse Timing
Twisted-Pair
Output
NOTE: Twisted-pair output default pins are as follows: DPAP/N_0 and DPBP/N_1.
Figure 36. FLP Burst Timing
Twisted-Pair
Output
NOTE: Twisted-pair output default pins are as follows: DPAP/N_0 and DPBP/N_1.
Table 48. Fast Link Pulse Timing Parameters
Parameter
Clock/Data pulse width
Clock pulse to Data pulse
Clock pulse to Clock pulse
FLP burst width
FLP burst to FLP burst
Clock/Data pulses per burst
1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to
production testing.
84
Clock Pulse
Data Pulse
t1
t1
t2
t3
FLP Burst
t4
t5
1
Sym
Min
Typ
t1
115
116
t2
55.5
63
t3
111
126
t4
2.0
t5
8
10
17
Clock Pulse
FLP Burst
Max
Units
Test Conditions
118
ns
69.5
s
139
s
ms
24
ms
33
ea
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002