SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 4

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SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
Contents
4.0
5.0
6.0
7.0
8.0
4
3.8
3.9
3.10
Application Information
4.1
4.2
4.3
4.4
4.5
Auto Negotiation
Auto MDI/MDIX
100 Mbps Operation
8.1
Configuration
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
100 Mbps Operation............................................................................................ 35
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
10 Mbps Operation.............................................................................................. 38
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
Monitoring Operations......................................................................................... 39
3.10.1 Monitoring Auto-Negotiation................................................................... 39
3.10.2 Per-Port LED Driver Functions............................................................... 39
Design Recommendations .................................................................................. 41
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
Typical Application Circuits ................................................................................. 44
Initialization ......................................................................................................... 47
MDIO Control Mode ............................................................................................ 47
Manual Control Mode.......................................................................................... 47
Displaying Symbol Errors.................................................................................... 53
Twisted-Pair Interface ............................................................................ 33
Fiber Interface ........................................................................................ 34
Fault Detection and Reporting ............................................................... 34
Remote Fault.......................................................................................... 34
Far End Fault ......................................................................................... 34
100BASE-X Network Operations ........................................................... 35
100BASE-X Protocol Sublayer Operations ............................................ 36
PCS Sublayer......................................................................................... 36
3.8.3.1 Preamble Handling.................................................................... 36
3.8.3.2 Dribble Bits ................................................................................ 36
PMA Sublayer ........................................................................................ 37
3.8.4.1 Link Failure Override ................................................................. 37
3.8.4.2 Carrier Sense ............................................................................ 37
3.8.4.3 Twisted-Pair PMD Sublayer ...................................................... 37
3.8.4.4 Scrambler/Descrambler............................................................. 37
3.8.4.5 Baseline Wander Correction ..................................................... 37
Fiber PMD Sublayer ............................................................................... 38
3.8.5.1 Far End Fault Indications .......................................................... 38
Polarity Correction.................................................................................. 38
Dribble Bits............................................................................................. 39
Link Test................................................................................................. 39
Link Failure............................................................................................. 39
Jabber .................................................................................................... 39
General Design Guidelines .................................................................... 41
Power Supply Filtering ........................................................................... 41
Power and Ground Plane Layout Considerations .................................. 42
4.1.3.1 Chassis Ground......................................................................... 42
MII Terminations .................................................................................... 42
The Fiber Interface................................................................................. 42
Twisted-Pair Interface ............................................................................ 43
4.1.6.1 Magnetics Information ............................................................... 43
............................................................................................................ 49
.......................................................................................................... 52
...................................................................................................... 51
................................................................................................ 53
......................................................................................... 41
Rev. Date: March 1, 2002
Document #: 249426
Revision #: 002
Datasheet

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