SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 77

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SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
15.0
Timing Diagrams
The LXT973 device meets all timings for MII per the IEEE 802.3u standard.
Table 32 on page 82
Figure 27. 100BASE-TX Transmit Timing - 4B Mode
TXCLK
TXD<3:0>
Twisted-Pair
NOTE: Twisted-pair output default pins are as follows: DPAP/N_0 and
Table 40. MII - 100BASE-TX Transmit Timing Parameters - 4B Mode
Parameter
TXD<3:0>, TXEN, TXER setup to
TXCLK High
TXD<3:0>, TXEN, TXER hold from
TXCLK High
TXEN sampled to CRS asserted
TXEN sampled to CRS de-asserted
TXEN sampled to twisted-pair output
(Tx latency)
1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to
production testing.
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
refer to MII timings.
0ns
t1
TXEN
t2
t5
Output
t3
CRS
DPBP/N_1.
Sym
Min
t1
12
t2
0
t3
2
t4
2
t5
Table 27
through
250ns
t4
Test
1
Typ
Max
Units
Conditions
ns
ns
4
5
BT
4
5
BT
5
BT
77

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