SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Table 3.
LXT973 Port 1 Signal Descriptions (Continued)
Pin #
Signal Names
3
COL1
4
CRS1
19
MDDIS1
22
MDC1
23
MDIO1
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
Table 4.
LXT973 Network Interface Signal Descriptions
Signal
Pin #
Names
59
DPAP_0
TX+
60
DPAN_0
63
DPBP_0
RX+
64
DPBN_0
RX-
76
SD0
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
ST = Schmitt Triggered input, TS = Tri-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
18
1
Type
Collision Detected. The LXT973 asserts this output when a collision
O, TS
is detected. This output remains High for the duration of the collision.
COL is asynchronous and is inactive during full-duplex operation.
Carrier Sense. During half-duplex operation, the LXT973 asserts this
output when either the transmit or receive medium is non-idle. During
O, TS
full-duplex operation, CRS1 is asserted only when receive medium is
non-idle.
Management Disable. When MDDIS is tied High, the MDIO port is
completely disabled and the Hardware Control Interface pins set their
respective bits at power-up and reset.
When MDDIS is pulled Low at power-up or reset via the internal pull-
I
down resistor or by tieing it to ground, the Hardware Control Interface
Pins control only the initial or “default” values of their respective
register bits. After the power-up/reset cycle is complete, bit control
reverts to the MDIO serial channel.
Management Data Clock. Clock for MDIO1 serial channel. Maximum
frequency is 20 MHz.
I
20 MHz value to be verified prior to final production release
(Note:
of product.)
Management Data Input/Output. Bidirectional serial data channel for
I/O
PHY/STA communication.
TP
Fiber
Pair
1
Port
Type
Op
Op
Type
Twisted-Pair/Fiber Pair A, Positive &
Negative - Port 0. Differential pair produces
RX+
0
A
AI/AO,
or receives IEEE 802.3-compliant pulses for
SL
TX-
RX-
0
A
either 100BASE-TX or 10BASE-T.
Also acts as receiver in Fiber mode.
Twisted-Pair/Fiber Pair B, Positive &
Negative - Port 0. Differential pair produces
TX+
0
B
AI/AO,
or receives IEEE 802.3-compliant pulses for
SL
TX-
0
B
either 100BASE-TX or 10BASE-T.
Also acts as transmitter in Fiber mode.
Signal Detect. This signal is used for signal
-
-
-
-
I
quality indication in Fiber mode. In twisted-
pair mode, this pin should be tied Low.
Signal Description
Signal Description
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002