SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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3.5.5
Hardware Configuration Settings
The LXT973 provides a hardware option to set the initial device configuration. The hardware
option uses four per-port configuration pins that provide control (see
Table 9. Configuration Settings (Hardware Control Interface)
FIBER/TPx
AUTO-NEGx
Low
-
Low
-
High
High
High
High
High
High
High
High
High
Low
High
Low
High
Low
High
Low
1. These pins also set the default values for Registers 0 and 4 accordingly.
3.6
Link Establishment
3.6.1
Auto-Negotiation
The LXT973 attempts to auto-negotiate with its link partner by sending Fast Link Pulse (FLP)
bursts. Each burst consists of 33 pulse positions spaced 62.5 s apart. Odd link pulses (clock
pulses) are always present. Even link pulses (data pulses) may also be present or absent to indicate
a “1” or a “0”. Each FLP burst exchanges 16 bits of data, referred to as a “page.” All devices that
support auto-negotiation must implement the “Base Page”, defined by IEEE 802.3 (Registers 4 and
5). The LXT973 also supports the optional “Next Page” function (Registers 7 and 8).
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
SPEEDx
DUPLEXx
100BASE-FX is enabled in half-duplex mode.
-
Low
Auto-negotiation is disabled.
100BASE-FX is enabled in full-duplex mode.
-
High
Auto-negotiation is disabled.
AUTO_NEG is enabled. All capabilities are
High
High
advertised.
Register bits 4.8, 4.7, 4.6, and 4.5 are all set to 1.
AUTO_NEG is enabled. Only 100 Mbps
capabilities are advertised.
High
Low
Register bits 4.8 and 4.7 are set 1. Register bits
4.6 and 4.5 are cleared to 0.
AUTO_NEG is enabled. Only 10 Mbps capability is
advertised.
Low
High
Register bits 4.8 and 4.7 are cleared to 0. Register
bits 4.6 and 4.5 are set to 1.
AUTO_NEG is enabled. Only half -duplex
capability is advertised.
Low
Low
Register bits 4.7 and 4.5 are set 1. Register bits
4.8 and 4.6 are cleared to 0.
AUTO_NEG is disabled. LXT973 port x is forced to
High
High
100 Mbps full-duplex operation.
AUTO_NEG is disabled. LXT973 port x is forced to
High
Low
100 Mbps half-duplex operation.
AUTO_NEG is disabled. LXT973 port x is forced to
Low
High
10 Mbps full-duplex operation.
AUTO_NEG is disabled. LXT973 port x is forced to
Low
Low
10 Mbps half-duplex operation.
Table 9 on page
31).
Mode
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