SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Table 21. Auto-Negotiation Advertisement Register (Address 4)
Bit
Name
4.15
Next Page
4.14
Reserved
4.13
Remote Fault
4.12
Reserved
Asymmetric
4.11
Pause
4.10
Pause
4.9
100BASE-T4
100BASE-TX
4.8
Full-Duplex
4.7
100BASE-TX
10BASE-T
4.6
Full-Duplex
4.5
10BASE-T
Selector Field,
4.4:0
S<4:0>
1. Refer to
Table 16 on page 61
2. Register bits 4.10 and 4.8:5 are initialized based on the pin configuration value.
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Description
1 = PHY is capable of Next Page exchanges
0 = PHY is not capable of Next Page exchanges
Write as 0, ignore on read
1 = Remote fault.
0 = No remote fault.
Write as 0, ignore on read
Pause operation defined in Clause 40 and 27
Pause operation defined per IEEE 802.3x standard
1 = 100BASE-T4 capability is available.
0 = 100BASE-T4 capability is not available.
(The LXT973 does not support 100BASE-T4 but
allows this bit to be set to advertise in the auto-
negotiation sequence for 100BASE-T4 operation. An
external 100BASE-T4 transceiver may be switched
in, if this capability is desired.)
1 = DTE is 100BASE-TX full-duplex capable.
0 = DTE is not 100BASE-TX full-duplex capable.
1 = DTE is 100BASE-TX capable.
0 = DTE is not 100BASE-TX capable.
1 = DTE is 10BASE-T full-duplex capable.
0 = DTE is not 10BASE-T full-duplex capable.
1 = DTE is 10BASE-T capable.
0 = DTE is not 10BASE-T capable.
<00001> = IEEE 802.3
<00010> = IEEE 802.9 ISLAN-16T
<00000> = Reserved for future auto-negotiation
development
<11111> = Reserved for future auto-negotiation
development
Unspecified or reserved combinations should not be
transmitted.
Note: The selector field can be programmed to any
value. In order for auto-negotiation to complete, the
link partner’s received selector field must match the
value programmed in this register.
for Register Bit Descriptions.
1
Type
Default
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
R/W
Note 2
0
R/W
Note 2
0
R/W
Note 2
0
R/W
Note 2
R/W
00001
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