SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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Note: The LXT973 does not support fiber connections at 10 Mbps.
3.9.2
Dribble Bits
The LXT973 device handles dribble bits in all modes. If one through four dribble bits are received,
the nibble is passed across the MII. If five through seven dribble bits are received, the second
nibble is not sent to the MII bus.
3.9.3
Link Test
The LXT973 always transmits link pulses in 10BASE-T mode. When enabled, the link test
function monitors the connection for link pulses. Once link pulses are detected, data transmission is
enabled and remains enabled as long as either the link pulses or data transmission continues. If link
pulses stop, the data transmission is disabled.
If the link test function is disabled, the LXT973 transmits to the connection regardless of detected
link pulses. The link test function is disabled by setting Register bit 16.14 = 1.
3.9.4
Link Failure
Link failure occurs if Link Test is enabled and link pulses or packets stop being received. If this
condition occurs, the LXT973 returns to the auto-negotiation phase if auto-negotiation is enabled.
3.9.5
Jabber
If a transmission exceeds the jabber timer, the LXT973 disables the transmit and loopback
functions. The LXT973 automatically exits jabber mode after the unjab time has expired. This
function is disabled by setting Register bit 16.10 = 1.
3.10
Monitoring Operations
3.10.1
Monitoring Auto-Negotiation
Auto-negotiation may be monitored as follows:
Link Status Register bit 1.2 = 1 once the link is established.
Additional bits in Register 1 can be used to determine the link operating conditions and status
(refer to
Table 18 on page
3.10.2
Per-Port LED Driver Functions
The LXT973 incorporates three direct drive LEDs per port (LEDn_1, LEDn_2, and LEDn_3). On
power-up, all the LEDs light up for approximately one second after reset de-asserts. Each LED
may be configured to one of several different display modes using the LED Configuration Pins, as
shown in
Table 10 on page
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
63).
40.
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