SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 

Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
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LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
7.0
Auto MDI/MDIX
Twisted-pair Ethernet PHYs must be correctly configured for MDI or MDIX operation to inter
operate. This has historically been accomplished using special patch cables, magnetics pinouts, or
PCB wiring.
The LXT973 PHY supports the automatic MDI/MDIX configuration originally developed for
1000BASE-T and standardized in IEEE 802.3u, section 40. A manual configuration (for example,
non-automatic) is still possible using configuration register bits. The automatic MDI/MDIX
function is not intended for fiber applications.
The automatic MDI/MDIX state machine facilitates switching of the twisted-pair input signals
(DPBP/N_0 and DPAP/N_1) with the twisted-pair output signals (DPAP/N_0 and DPBP/N_1),
respectively, prior to the auto-negotiation mode of operation. This is done so that FLPs can be
transmitted and received in compliance with Clause 28, Auto-Negotiation specifications.
The correct polarization of the crossover circuit is determined by an algorithm that controls the
switching function. This algorithm uses an 11-bit Linear Feedback Shift Register (LFSR) to create
a pseudo-random sequence that each end of the link uses to determine its proposed configuration.
After selecting MDI or MDIX, the node waits for a specified amount of time, while evaluating its
receive channel, to determine whether the other end of the link is sending link pulses or PHY-
dependent data. If link pulses or PHY-dependent data are detected, it remains in that configuration.
If link pulses or PHY-dependent data are not detected, it increments its LFSR and makes a decision
to switch based on the value of the next bit. The state machine does not move from one state to
another while link pulses are being transmitted.
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Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002