SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 3

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SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
Contents
1.0
2.0
3.0
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
Pin Assignments and Signal Descriptions
Signal Descriptions
Functional Description
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Introduction..........................................................................................................22
3.1.1
Interface Descriptions..........................................................................................22
3.2.1
MII Operation.......................................................................................................24
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
Operating Requirements .....................................................................................28
3.4.1
3.4.2
Initialization..........................................................................................................29
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
Link Establishment ..............................................................................................31
3.6.1
Network Media/Protocol Support.........................................................................33
3.7.1
Comprehensive Functionality .................................................................22
10/100 Mbps Network Interface .............................................................22
3.2.1.1 Twisted-Pair Interface ...............................................................23
3.2.1.2 MDI Crossover (MDIX) ..............................................................23
3.2.1.3 Fiber Interface ...........................................................................24
MII Clocks...............................................................................................24
Transmit Enable .....................................................................................24
Receive Data Valid.................................................................................24
Carrier Sense .........................................................................................25
Error Signals...........................................................................................25
Collision..................................................................................................25
Loopback................................................................................................25
3.3.7.1 Operational Loopback ...............................................................25
3.3.7.2 Test Loopback ...........................................................................25
Configuration Management Interface .....................................................26
3.3.8.1 MII Management Interface ........................................................26
3.3.8.2 MII Addressing ..........................................................................27
3.3.8.3 Hardware Control Interface .......................................................28
Power Requirements..............................................................................28
Clock Requirements ...............................................................................28
3.4.2.1 Reference Clock / External Oscillator........................................28
3.4.2.2 MDIO Clock ...............................................................................29
MDIO Control Mode ...............................................................................29
Hardware Control Mode .........................................................................29
Power-Down Mode.................................................................................29
3.5.3.1 Hardware Power-Down .............................................................30
3.5.3.2 Software Power-Down...............................................................30
Reset ......................................................................................................30
Hardware Configuration Settings ...........................................................31
Auto-Negotiation.....................................................................................31
3.6.1.1 Base Page Exchange................................................................32
3.6.1.2 Next Page Exchange.................................................................32
3.6.1.3 Controlling Auto-Negotiation .....................................................32
3.6.1.4 Link Criteria ...............................................................................32
3.6.1.5 Parallel Detection ......................................................................32
10/100 Mbps Network Interface .............................................................33
.................................................................................................16
...........................................................................................22
....................................................12
Contents
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