SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 58

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SLXT973QC.A2

Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet

Specifications of SLXT973QC.A2

Lead Free Status / RoHS Status
Not Compliant
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
10.6
10.7
10.8
58
Dribble Bits
The LXT973 device handles dribbles bits. If one to four dribble bits are received, the nibble is
passed across the interface. The data passed across is padded with ones, if necessary. If five to
seven dribble bits are received, the second nibble is not sent to the MII bus. This ensures that
dribble bits one through seven will not cause a MAC to discard the frame due to a CRC error. (In
10 Mbps serial mode, all bits are simply passed across the interface unmodified.)
Transmit Polarity Control
The LXT973 allows control over 10BASE-T transmit signal polarity for simplified integration. In
combination with selectable MDI/MDIX mode and automatic polarity detection, this allows
maximum flexibility in pinout definition. (Either of the twisted pairs may be transmit or receive,
and either side of each twisted pair may be set to positive or negative.)
PHY Address
The LXT973 provides four bits to set the PHY address.The least significant bit is fixed internally
with Port 1 always being one address higher than Port 0.
Rev. Date: March 1, 2002
Document #: 249426
Revision #: 002
Datasheet

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