SLXT973QC.A2

Manufacturer Part NumberSLXT973QC.A2
ManufacturerIntel
SLXT973QC.A2 datasheet
 


Specifications of SLXT973QC.A2

Lead Free Status / RoHS StatusNot Compliant  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Page 58/88

Download datasheet (2Mb)Embed
PrevNext
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
10.6
Dribble Bits
The LXT973 device handles dribbles bits. If one to four dribble bits are received, the nibble is
passed across the interface. The data passed across is padded with ones, if necessary. If five to
seven dribble bits are received, the second nibble is not sent to the MII bus. This ensures that
dribble bits one through seven will not cause a MAC to discard the frame due to a CRC error. (In
10 Mbps serial mode, all bits are simply passed across the interface unmodified.)
10.7
Transmit Polarity Control
The LXT973 allows control over 10BASE-T transmit signal polarity for simplified integration. In
combination with selectable MDI/MDIX mode and automatic polarity detection, this allows
maximum flexibility in pinout definition. (Either of the twisted pairs may be transmit or receive,
and either side of each twisted pair may be set to positive or negative.)
PHY Address
10.8
The LXT973 provides four bits to set the PHY address.The least significant bit is fixed internally
with Port 1 always being one address higher than Port 0.
58
Datasheet
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002