EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 10

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Transceivers
2–2
Stratix II GX Device Handbook, Volume 1
There are up to 20 transceiver channels available on a single Stratix II GX
device.
serial bandwidth for each Stratix II GX device.
Figure 2–2
transceiver channels, supporting logic, and I/O buffers. Each transceiver
channel consists of a receiver and transmitter. The supporting logic
contains two transmitter PLLs to generate the high-speed clock(s) used by
the four transmitters within that block. Each of the four transmitter
channels has its own individual clock divider. The four receiver PLLs
within each transceiver block generate four recovered clocks. The
transceiver channels can be configured in one of the following functional
modes:
■
■
■
■
■
■
■
■
■
EP2SGX30C
EP2SGX60C
EP2SGX30D
EP2SGX60D
EP2SGX60E
EP2SGX90E
EP2SGX90F
EP2SGX130G
Table 2–1. Stratix II GX Transceiver Channels
PCI Express (PIPE)
OIF CEI PHY Interface
SONET/SDH
Gigabit Ethernet (GIGE)
XAUI
Basic (600 Mbps to 3.125 Gbps single-width mode and 1 Gbps to
6.375 Gbps double-width mode)
SDI (HD, 3G)
CPRI (614 Mbps, 1228 Mbps, 2456 Mbps)
Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps)
Device
Table 2–1
shows the elements of the transceiver block, including the four
shows the number of transceiver channels and their
Number of Transceiver
Channels
12
12
16
20
4
4
8
8
Serial Bandwidth
(Full Duplex)
Altera Corporation
102 Gbps
102 Gbps
153 Gbps
153 Gbps
204 Gbps
255 Gbps
51 Gbps
51 Gbps
October 2007