EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 72

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

MultiTrack Interconnect
Figure 2–46. R4 Interconnect Connections
Notes to
(1)
(2)
(3)
2–64
Stratix II GX Device Handbook, Volume 1
C4 and C16 interconnects can drive R4 interconnects.
This pattern is repeated for every LAB in the LAB row.
The LABs in
Figure
2–46:
Figure 2–46
R4 Interconnect
show the 16 possible logical outputs per LAB.
Driving Left
The direct link interconnect allows a LAB, DSP block, or TriMatrix
memory block to drive into the local interconnect of its left and right
neighbors and then back into itself, providing fast communication
between adjacent LABs and/or blocks without using row interconnect
resources.
The R4 interconnects span four LABs, three LABs and one M512 RAM
block, two LABs and one M4K RAM block, or two LABs and one DSP
block to the right or left of a source LAB. These resources are used for fast
row connections in a four-LAB region. Every LAB has its own set of R4
interconnects to drive either left or right.
interconnect connections from a LAB.
R4 interconnects can drive and be driven by DSP blocks and RAM blocks
and row IOEs. For LAB interfacing, a primary LAB or LAB neighbor can
drive a given R4 interconnect. For R4 interconnects that drive to the right,
the primary LAB and right neighbor can drive onto the interconnect. For
R4 interconnects that drive to the left, the primary LAB and its left
neighbor can drive onto the interconnect. R4 interconnects can drive
other R4 interconnects to extend the range of LABs they can drive. R4
interconnects can also drive C4 and C16 interconnects for connections
from one row to another. Additionally, R4 interconnects can drive R24
interconnects.
Adjacent LAB can
Drive onto Another
LAB's R4 Interconnect
Neighbor
LAB
Notes
Primary
LAB (2)
(1), (2),
(3)
C4 and C16
Column Interconnects (1)
Neighbor
LAB
Figure 2–46
R4 Interconnect
Driving Right
shows R4
Altera Corporation
October 2007