EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 58

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Adaptive Logic Modules
2–50
Stratix II GX Device Handbook, Volume 1
f
One ALM contains two programmable registers. Each register has data,
clock, clock enable, synchronous and asynchronous clear, asynchronous
load data, and synchronous and asynchronous load/preset inputs.
Global signals, general-purpose I/O pins, or any internal logic can drive
the register’s clock and clear control signals. Either general-purpose I/O
pins or internal logic can drive the clock enable, preset, asynchronous
load, and asynchronous load data. The asynchronous load data input
comes from the datae or dataf input of the ALM, which are the same
inputs that can be used for register packing. For combinational functions,
the register is bypassed and the output of the LUT drives directly to the
outputs of the ALM.
Each ALM has two sets of outputs that drive the local, row, and column
routing resources. The LUT, adder, or register output can drive these
output drivers independently (see
drivers, two ALM outputs can drive column, row, or direct link routing
connections, and one of these ALM outputs can also drive local
interconnect resources. This allows the LUT or adder to drive one output
while the register drives another output. This feature, called register
packing, improves device utilization because the device can use the
register and the combinational logic for unrelated functions. Another
special packing mode allows the register output to feed back into the LUT
of the same ALM so that the register is packed with its own fan-out LUT.
This feature provides another mechanism for improved fitting. The ALM
can also drive out registered and unregistered versions of the LUT or
adder output.
See the
more information on the efficiencies of the Stratix II GX ALM and
comparisons with previous architectures.
ALM Operating Modes
The Stratix II GX ALM can operate in one of the following modes:
■
■
■
■
Each mode uses ALM resources differently. Each mode has 11 available
inputs to the ALM (see
local interconnect; carry-in from the previous ALM or LAB; the shared
arithmetic chain connection from the previous ALM or LAB; and the
register chain connection—are directed to different destinations to
implement the desired logic function. LAB-wide signals provide clock,
Normal mode
Extended LUT mode
Arithmetic mode
Shared arithmetic mode
Stratix II Performance and Logic Efficiency Analysis White Paper
Figure
2–35)—the eight data inputs from the LAB
Figure
2–36). For each set of output
Altera Corporation
October 2007
for