EP2SGX90EF1152C4N Altera, EP2SGX90EF1152C4N Datasheet - Page 133

• Manufacturer Part Number: EP2SGX90EF1152C4N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C4N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1767; EP2SGX90EF35C4NES

Altera Corporation
October 2007
Table 2–32
strength control.
Open-Drain Output
Stratix II GX devices provide an optional open-drain (equivalent to an
open collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (for example, interrupt
and write enable signals) that can be asserted by any of several devices.
Bus Hold
Each Stratix II GX device I/O pin provides an optional bus-hold feature.
The bus-hold circuitry can hold the signal on an I/O pin at its last-driven
state. Since the bus-hold feature holds the last-driven state of the pin until
the next input signal is present, an external pull-up or pull-down resistor
is not needed to hold a signal level when the bus is tri-stated.
Note to
(1)
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
Table 2–32. Programmable Drive Strength
The Quartus II software default current setting is the maximum setting for each
I/O standard.
I/O Standard
Table
shows the possible settings for the I/O standards with drive
2–32:
I
Setting (mA) for Column
OH
24, 20, 16, 12, 8, 4
24, 20, 16, 12, 8, 4
/ I
12, 10, 8, 6, 4, 2
OL
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
20, 18, 16, 8
16, 12, 8, 4
20, 18, 16
20, 18, 16
24, 20, 16
Current Strength
8, 6, 4, 2
I/O Pins
12, 8
Stratix II GX Device Handbook, Volume 1
Note (1)
Stratix II GX Architecture
I
OH
Setting (mA) for Row
/ I
OL
12, 10, 8, 6, 4
10, 8, 6, 4
Current Strength
8, 6, 4, 2
I/O Pins
12, 8, 4
12, 8, 4
8, 6, 4
12, 8
8, 4
4, 2
16
—
—
—
2–125